Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

Also,

Can you dump the entire boot text from power up to hang? Would like to see all the commands executed by the bootloader.

-Mike

Good point. I'll defer any FPGA programming until I resolve the linux kernel load.

Here's the boot text. You can see the auto FPGA programming in the text. I'll turn that off and try again,

OMAP-L138/AM-1808/AM-1810 initialization passed!
Configuring 128MB mDDR
Booting TI User Boot Loader
UBL Version: 1.65:2.28.1 BuiltJul 11 2011 12:49:53
UBL Flashtype: SPI
Starting SPI Memory Copy...
Valid magicnum, 0x55424CBB, found at offset 0x00010000.
DONE
Jumping to entry point at 0xC1080000.

U-Boot 2009.11 (Mar 31 2011 - 19:39:18)

I2C: ready
DRAM: 128 MB
NAND: 256 MiB
MMC: davinci: 0
In: serial
Out: serial
Err: serial
ARM Clock : 300000000 Hz
DDR Clock : 150000000 Hz
EMIFA CLock : 100000000 Hz
DSP Clock : 300000000 Hz
ASYNC3 Clock : 150000000 Hz
Enet config : 2
MMC 0 Enable : 0
Resetting ethernet phy
8192 KiB M25P64 at 0:0 is now current device
Loading FPGA from 0xC0700000 with 0x170000 bytes
Loading FPGA done
Net: Ethernet PHY: GENERIC @ 0x03 [0x8]

1. Booting kernel from Legacy Image at c0700000 ...
   Image Name: Linux-2.6.34-rc1-07430-g2e70fb6
   Image Type: ARM Linux Kernel Image (uncompressed)
   Data Size: 1818012 Bytes = 1.7 MB
   Load Address: c0008000
   Entry Point: c0008000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK
   OK

Starting kernel ...

Hi Craig,

Just following up. Are you still DOA? Or did not programming the FPGA clear the issue?

-Mike

Hey Mike,

Late yesterday I booted into UBOOT; cleared the bootfpga (setenv bootfpga;saveenv); rebooted with Angstrom image and still got stuck at "Starting kernel..."

I tried twice just to make sure I did NOT get FPGA DONE LED.

This weekend I'm planning to try a few more things: the other uImage file I have, extracting release_2011-03-31.run and trying that uImage.

Late yesterday I burned the latest Ubuntu iso to CD. I think running Ubuntu is the only way to extract a .run file.

Thanks,
Craig

Hi Craig,

I am attaching a uImage file built for the Industrial I/O board from our kernel code baseline.

This really should work for your set up, assuming you are using an Industrial I/O baseboard.

Your steps should also get you an image that should work as well, but I'd like to ensure that your gear is OK if possible.

-Mike

Thanks Mike.

My plan is to also extract the image from the .run file and try both this afternoon.

I am using the Industrial I/O baseboard.

I would also be interested in building an image from source. As you indicated yesterday there is a release planned for the coming week.

Craig

The uImage_Indio_20110723 kernel image booted but could not mount to a filesystem.

Getting closer!

I attached the full bootlog.

Hi Craig,

I think you need to modify the bootargs assuming the NAND has a valid filesystem on it.

See this wiki page.

Specifically, you need the "rootfstype=jffs2" part of the bootargs added.

You might want to set up booting via nfs if you are just starting development.

-Mike

Success has been achieved. Thanks Mike!

I loaded the stock uImage from the .run file supplied with the kit. That did the trick - I can now startup the board, it flushes and then automatically loads the FPGA during boot all the way to Linux.

And I didn't lose the filesytem. Which brings me to my next questions. [Is there a prize for number/volume of questions?]

Is there a memory map I can look at? It's not clear to me yet what is loaded where. For example, out of the box what's in NOR flash? NAND flash? I'm happy to create one but might need some guidance of commands to issue.

I opened this project file in XISE and it yelled at me for a number of VHD files (see attached png).

example.zip - XISE project and source for IndustrialIO.bin - LX45 Industrial IO Board FPGA (no display support) (60.1 KB)

Is this what Greg was referring to by: "You'll need to link against our cores in order to build this project, and those can be found in the latest MDK release."

Meaning I already have thess VHD files?

Hi Craig,

Yeah, the Xilinx ISE file format really doesn't use relative path names very well.

As far as the VHDL, all of the common/base VHDL needed to build the top level (EMIF interface, the base module, the core_version module, etc.) is included in the fpga/vhdl directory of the Board Support Package.

For provided cores (e.g., UART, SPI, I2C), our policy is to distribute them in netlist form at this time (in the fpga/cores/build_spartan6 folder). The component/port declarations for each core are included in the MityDSP package vhdl file in the fpga/vhdl directory. To pick up the netlists, you need to either add them directly to your project or in the options for implementation add the path to them to the "macro search path".

-Mike

Thanks Mike. I picked up the common VHDL files with no trouble.

However, when I tried to add a netlist file (.ngc?), I got an error that indicates a different FPGA than I have (for which the project was built).

How can I get the correct netlists?

I successfully built this project but I had to comment out anything related to pwm. Seems I do not have the pwm.ngc netlist file. Also generated the correct .bin file same as what you guys provided.

The pwm.ngc should be included in the 2011-08-01 MDK release (just published).

-Mike

Hi

What was the solution to the last problem (add source error)? I get the same warning when trying to add pwm.ngc etc into a lx45 project.

thanks, Flemming