FPGA Unused Pins
Added by John Mladenik about 14 years ago
Did you have to do anything special to the unused EMIFA pins like
I_EMA_CS0_N
I_EMA_CS3_N
I_EMA_CS5_N
I_EMA_CAS
I_EMA_RAS
I_EMA_SDCKE
I_EMA_RNW
to insure that the FPGA does not interfere with the EMIFA bus?
I have loaded the FPGA using the Xilinx programmer and tested the FPGA memory space using uboot memory routines adn didnt have a problem but when our software guys loads our FPGA image they get problems. Here is what they said:
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We just need to check something with Dennis. IIRC, he says that when the board is programmed using the Critical Link bin file, everything works. But when he programs using the one you sent, the board has problems reading the boot volume.
This happens either when he programs using the UBoot system or using the utility program that runs under the on-board Linux. If he reprograms via UBoot, the board won't even boot. If he reprograms using the Linux utility, the file system subsequently becomes corrupted enough that pieces of it are unreadable. The visible effect of this is that some of the OS software "disappears" from the virtual disk drive. The OS can't see the files any more.
We've seen this sort of phenomenon before, on machines where the HD is failing. It's usually due to holes being blown in the file system's data structures at the hardware level. In other words, some sectors of the virtual HD simply are no longer readable.
The inability to boot at all when programming from UBoot is consistent with this theory. In that case, some of the low-level boot utilities needed to start up the OS are also blown away. This doesn't show up when using the Linux utility only because the system has already booted by then.
Our theory is that something in the FPGA image that you've sent is causing part of the virtual HD to become unreadable. We don't think it's a programming software issue since two different programming mechanisms encounter a similar failure. We'll be happy to do additional experiments to nail this down more precisely. Let us know what we can do. Thanks.Replies (2)
RE: FPGA Unused Pins - Added by Michael Williamson about 14 years ago
Hi John,
In general, you should tri-state / float all unused pins on the FPGA. This will result in those pins behaving the same as when the FPGA is not programmed (e.g., during power up, etc.). Any pins connected between the FPGA and the on-module circuits (the OMAP processor, for example) are appropriately pulled up or down by external resistors in order to ensure proper behavior.
I believe that, by default, the Xilinx configuration options assign unused pins to pulled down, which would cause major problems with the NAND interface (as the NAND bus lines are the EMIFA bus lines and are connected to the FPGA).
You can check the settings under the Xilinx ISE Generate Programming File -> Process Properties -> Configuration Options dialog. There is an Unused IOB Pins option, make sure this is set to "float".
-Mike
