Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

Hello Brian,

Are you trying to manually by hand create the DTS or are you using the Altera Sopc2dts tool that will take the output of your quartus build and create the DTS for you?

We normally go about creating the DTS by hand. The DTS for our 5CSE development kit has an example of adding FPGA GPIO cores to the device tree. It can be found at: socfpga_mitysom5cse_devkit.dts

The cores are defined here:

        hps_lw_bus: bus@0ff200000 {
            status = "okay";

            sysid_qsys: sysid@000000 {
                compatible = "altr,sysid-1.0";
                reg = <0x000000 0x08>;
            };

            pio_0: gpio@0020 {
                compatible = "altr,pio-1.0";
                reg = <0x0020 0x20>;
                interrupts = <0 40 4>;
                altr,gpio-bank-width = <32>;
                altr,interrupt_type = <IRQ_TYPE_EDGE_RISING>;
                #gpio-cells = <1>;
                gpio-controller;
                #interrupt-cells = <1>;
                interrupt-controller;
            };

            pio_1: gpio@0040 {
                compatible = "altr,pio-1.0";
                reg = <0x0040 0x20>;
                interrupts = <0 41 4>;
                altr,gpio-bank-width = <32>;
                altr,interrupt_type = <IRQ_TYPE_EDGE_RISING>;
                #gpio-cells = <1>;
                gpio-controller;
                #interrupt-cells = <1>;
                interrupt-controller;
            };

            pio_2: gpio@0060 {
                compatible = "altr,pio-1.0";
                reg = <0x0060 0x20>;
                interrupts = <0 42 4>;
                altr,gpio-bank-width = <32>;
                altr,interrupt_type = <IRQ_TYPE_EDGE_RISING>;
                #gpio-cells = <1>;
                gpio-controller;
                #interrupt-cells = <1>;
                interrupt-controller;
            };

            pio_3: gpio@0080 {
                compatible = "altr,pio-1.0";
                reg = <0x0080 0x20>;
                interrupts = <0 43 4>;
                altr,gpio-bank-width = <29>;
                altr,interrupt_type = <IRQ_TYPE_EDGE_RISING>;
                #gpio-cells = <1>;
                gpio-controller;
                #interrupt-cells = <1>;
                interrupt-controller;
            };
        };

We use a hierarchical DTS structure so the hps_lw_bus is defined in: socfpga_mitysom5cs.dtsi.

The following will do the address translation to the HPS light weight bus, allowing for your core definitions to be zero based address, like seen in qsys.

        hps_lw_bus: bus@0ff200000 {
            compatible = "simple-bus";
            reg = <0xFF200000 0x00200000>;
            #address-cells = <1>;
            #size-cells = <1>;
            ranges = <0x0 0xFF200000 0x00200000>;
            status = "disabled";
        };

If you're using sopc2dts, we don't have too much familiarity with it here but if you'd like to post your DTS I can take a look and see if I can see anything out of order with it.

Dan

Hello Dan,

Thanks for the timely reply. Yes, I was using the Altera Sopc2dts tool to generate the DTB. I have rebuilt the project based on the .dts that you specified above. I was able to get past the Loading Kernel.

I have another issue with the boot where it hangs for about 2-3 minutes at "Starting system log daemon...1" , then fails the daemon process. The boot process will finish after that. But it fails to obtain an IP address and ifconfig give the following-- Warning: cannot open /proc/net/dev (No such file or directory). Limited output.

I only added Altera UART device support to the Kernel configuration.

I attached the boot log for reference.

Thanks,

Brian

Hi Brian,

It appears that all these issues are stemming from the SOM not being able to mount /proc. Can you make sure that CONFIG_PROC_FS is enabled in your defconfig? Also would you mind doing a quick diff of the .config and mitysom5csx_devkit_defconfig, just for a quick sanity check to see that the only change was the addition of the UART driver?

Dan

Hello Dan,

Yea, I agree. It looks like the mount /proc is causing issues. CONFIG_PROC_FS is enabled in both the defconfig and .config. Attached are snippets from the diff test and enabled PROC_FS.

Thanks,

Brian

Hello,

So, it seems that the attempt to mount /proc was denied because of the permission settings for the rootfs.tgz. I have been able to pass that stage but after boot I still don't obtain network interface configuration.

Could you post a link to a bootable SD card image that will work with my dev board??? The image I downloaded "sd_image_mitysom_5cse-l2-3y8_dev_kit.bin" from https://support.criticallink.com/redmine/attachments/download/9458/MitySOM_5CSE_L2_3Y8_Dev_Kit_Release_1.zip boots but dosent obtain full network configuration either... See attached boot log.

Thanks,

Brian

Hello Brian,

That is very odd that you are still seeing that error with the sd_image_mitysom_5cse-l2-3y8_dev_kit.bin. I just double checked that image and was not able to recreate the errors in your boot log, it booted an got an IP as expected.

In order to flash the image did you follow these instruction: Writing the SD Card Image ?

Sorry for the basic question, just trying to narrow things down a bit.

Dan

Dan,

SOLVED!!!

I found it strange that the sd_image_mitysom_5cse-l2-3y8_dev_kit.bin did not properly boot also. So I pulled another SD card from a different dev board and wrote the image to it, and it properly booted. Then I loaded my custom FPGA configuration, Kernel and supporting files and all booted. The dev kit is now up and running as expected.

Also got my custom image on the faulty card after a format.

Thanks again for all your support!

Brian

Glad to hear you got it working!

Dan