eMMC and bus width 8

Hi
Has anyone managed to interface an eMMC using 8 bit?
According to Cyclone V HPS "MMC Support matrix": https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/mmc-support-matrix.html 8 bit bus and 50MHz clock is supported, i.e. 50Mbytes/s.

I have updated the HPS with 8 bit for the SD/MMC controller and generated a new preloader and bootloader.
In the dts file I have changed from 4 to 8 bit:

&mmc {
    status = "okay";
    num-slots = <1>;
    broken-cd;
    cap-mmc-highspeed;
    cap-sd-highspeed;
    vmmc-supply = <&regulator_3_3v>;
    vwmmc-supply= <&regulator_3_3v>;
    bus-width = <8>;
};

The kernel starts but hangs after a few secs with "mmcblk0: error -115 sending stop command, original cmd response 0x900, card status 0xe00"

...
...
[    2.621256] Synopsys Designware Multimedia Card Interface Driver
[    2.627673] dw_mmc ff704000.dwmmc0: IDMAC supports 32-bit address mode.
[    2.634385] dw_mmc ff704000.dwmmc0: Using internal DMA controller.
[    2.640553] dw_mmc ff704000.dwmmc0: Version ID is 240a
[    2.645835] dw_mmc ff704000.dwmmc0: DW MMC controller at irq 40,32 bit host data width,1024 deep fifo
[    2.678808] mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
[    2.708825] mmc0: mmc_rescan_try_freq: trying to init card at 400000 Hz
[    2.715508] dw_mmc ff704000.dwmmc0: 1 slots initialized
...
...
[    2.887583] Waiting for root device /dev/mmcblk0p2...
[    2.893099] mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 52000000Hz, actual 50000000HZ div = 0)
[    2.903395] mmc0: new high speed MMC card at address 0001
[    2.909521] mmcblk0: mmc0:0001 VM020 3.58 GiB
[    2.914200] mmcblk0boot0: mmc0:0001 VM020 partition 1 4.00 MiB
[    2.920256] mmcblk0boot1: mmc0:0001 VM020 partition 2 4.00 MiB
[    2.927269]  mmcblk0: p2 p4
[    3.034702] mmcblk0: error -115 sending stop command, original cmd response 0x900, card status 0xe00

Any suggestions on how to get the 8 bit interface up and running?
We are using the Rocko branch with kernel 4.9 RT.

BR
VJ

emmc.png (45.1 KB) emmc.png

Replies (3)

RE: eMMC and bus width 8 - Added by Daniel Vincelette 10 months ago

Hello,

We haven't tried interfacing to a 8 bit eMMC with the 5CSx SOM. Just to double check did you rebuild your preloader and u-boot when you made the 4 bit to 8 bit change in platform designer? Also are you able to boot to Linux if you use this eMMC in 4 bit mode?

Best regards,
Dan

RE: eMMC and bus width 8 - Added by V J 10 months ago

Hi Dan
Yes, the preloader and uboot has been rebuild after changing the interface in platform designer. If I change to 4 bit in the dts file everything works fine.
We are using Quartus 17.1.
BR
VJ

RE: eMMC and bus width 8 - Added by V J 10 months ago

Now it is working, there was something wrong with the pinning.
Steps:
1. Update Platform designer.
2. Update IO pinning for the four extra bits and compile the new FPGA code.
3. Rebuild preloader and bootloader.
4. Update device tree.

cat /sys/kernel/debug/mmc0/ios
 clock:          52000000 Hz
 vdd:            21 (3.3 ~ 3.4 V)
 bus mode:       2 (push-pull)
 chip select:    0 (don't care)
 power mode:     2 (on)
 bus width:      3 (8 bits)
 timing spec:    1 (mmc high-speed)
 signal voltage: 0 (3.30 V)
 driver type:    0 (driver type B)

BR
VJ

(1-3/3) Go to top

Project

General

Profile

Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V