Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

Hello,

We are currently in the process of updating our instructions for building the FPGA, bootloaders, and filesystem with latest major versions provided by Altera. These instructions will be tailored and tested for our SOM, which we will recommend customers starting from. Are you able to wait till next week for us to get our documenation uploaded?

For the FPGA project starting point did you use our reference project or the DE-Nano?

Thanks,
Dan

Hello Daniel,
I will wait for your response. I am working on HPS only at present.

Thanks,
Bhardwaj

Hi Daniel,
Can you please tell me why this error is coming while booting.
I am facing this issue from last 15 days. Please give some solution ASAP to this error.
Thanks,
Bhardwaj

Hello,

From the error it looks like the SPL isn't able to correctly read the MBR/Partition table on the SD card. This could be due to misconfiguration of the pinmux in your FPGA design. As a sanity check, could you try our Quartus 18.1 SD Card Image to verify that you can at least reach u-boot?Image can be found here: https://support.criticallink.com/redmine/attachments/download/27156/sdcard_5cse_h4_3ya_20201116.zip

If you're able to get to the u-boot prompt with that SD card image then it would help rule out an issue with a hardware issue between the SOM and baseboard.

Also, can you please post the SD card image that gives you this error? And can you please send your .qsys file for your project so I can take a look at your pinmux.

Thank you,
Dan

Hi Daniel,
I had the tested the booting by the link which you have mentioned. It is working but getting an error related to ethernet but the board is booted.
Is any FPGA code mandatory to boot the hps?
Can we boot the hps without FPGA code?
As am working with Intel fpgasoc for the first time can you explain the procedure to boot the board in detail.

Thanks,
Bhardwaj kotha

Hello,

The Altera Cyclone V SoC boot process involves several steps to initialize and start up the system. The Cyclone V SoC integrates an ARM-based Hard Processor System (HPS) with FPGA fabric, and the boot process encompasses both the HPS and the FPGA. Here’s a high-level overview of the boot process:

1. Pre-Boot and Reset¶

• Power-On Reset (POR): When the system is powered on, it undergoes a Power-On Reset to initialize the system's hardware components to their default states.
• Boot ROM: The Boot ROM, a small piece of read-only memory embedded in the HPS, executes first. It is responsible for initial hardware configuration and starting the boot process.

2. Boot Phases¶

The boot process can be divided into several phases:

Phase 0: Boot ROM Code¶

• Boot ROM Execution: The Boot ROM code is executed from on-chip memory, which includes basic initialization such as setting up the memory controller.
• Boot Source Detection: The Boot ROM determines the boot source, which can be SD/MMC, QSPI, NAND, or other supported storage devices.

Phase 1: Preloader¶

• Load Preloader: The Boot ROM loads the preloader from the SD Card's A2 partition and loads it into the SoC's on-chip RAM.
• Preloader Execution: The preloader initializes the DDR memory, sets up basic peripherals, and configure's the HPS IO's pinmux. These settings come from the Quartus build, so a FPGA build is required in order to build the preloader. The preloader then loads the next stage bootloader (U-Boot) for the SD Cards A2 partition.

Phase 2: U-Boot¶

• Load U-Boot: The preloader loads U-Boot from the boot source into the DDR memory.
• U-Boot Execution: U-Boot provides a richer environment for further initialization, device driver initialization, programming the FPGA, and boot script execution. It can load the Linux kernel, device tree, and start the boot sequence into Linux.

Phase 3: Linux Kernel¶

• Load Kernel: U-Boot loads the Linux kernel, device tree blob (DTB), starts the Linux boot sequence
• Kernel Execution: The kernel is decompressed and starts executing, initializing hardware components, and mounting the root filesystem.

Phase 4: User Space¶

• Init Process: The kernel starts the `init` process, which initializes user-space services and applications.
• System Ready: The system is fully operational and ready for user interaction or automated tasks.

Additional Details¶

• FPGA Configuration: The FPGA fabric is programmed in u-boot before starting the kernel. It's possible to not program the FPGA and boot to Linux but you need to make sure the kernel doesn't try to access anything in the FPGA. The configuration of the kernel communicating to the FPGA normally done by adding nodes to your device tree. The ARM normally use the Light Weight HPS to FPGA bridge to access cores in the fabric, this is at address 0xFF200000 in the ARM memory map. If you look at our development kit devicetree you delete or disable the hps_lw_bus node in order to stop the kernel from trying to access the FPGA. If you don't do this then the ARM will hang during boot because it's trying to access an unprogrammed FPGA.

Best regards,
Dan

Hi Daniel,
Thank you for providing the information regarding booting. I understand the process to boot the cyclone v board.
I had followed the process which is mentioned in [[https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_uboot_181]]. I changed the compiler to arm-none-eabi instead of arm-altera-eabi (SocEDS BSP editor compiler) and in Makefile the compiler path had changed to arm-none-eabi path then got the following error. Please guide me where missed. I am attaching images regarding the change made in SocEDS BSP editor , Makefile in preloader path and error while make command.

Hello,

You shouldn't need to update the compiler or path from the default that are filled out by the bsp-editor. Did you also run into errors when you used the default cross compiler that was choosen by the bsp-editor?

Best regards,
Dan

Hi Daniel,
Now am able to generate the boot files.

Thanks & Regards,
Bhardwaj