Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

Hello,

Can you share capture of your console so we can evaluate what commands you are using and exactly what errors are being reported?

As long as you do not exceed resources on the FPGA you should be able to add the required pio modules to get you to 256 gpios. However, am I misunderstanding that it sounds like you might be interested in just sending 256 bits of raw data from the HPS to the FPGA (i.e. the interface does not need to be GPIO)? Please let me know if that is the case and I can supply details on ways
more efficient than GPIO by which you might accomplish this.

Thanks,
Greg

Yes, I wanted to send the 256 BITS of raw data from HPS to FPGA. Can you give me the supplies for that.

The most straightforward way to do that would be to create your own Platform Designer Component with an Avalon Memory Mapped Slave interface. (See https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/creating-components.html for details on creating a custom Platform Designer Component). Then, in Platform Designer, connect you Avalon Memory Mapped Slave interface to the h2f_lw_axi_master on the hps component. Now writes to physical address (0xFF200000 + Avalon Memory Mapped Slave interface offset) in the ARM will result writes on this bus. Your custom VHDL file associated with your custom Platform Designer Component can then handle these accesses to control the GPIOs (the h2f_lw_axi_master bus is 32 bits wide, so 4 writes will allow you to get the 256 bits of raw data from the HPS to the FPGA).

Thanks,
Greg

Hi,

In my implementation, the Avalon Memory Mapped interface automatically assigned a base address in platform designer with that address only I successfully sent an 32bit incremental data from the HPS to the FPGA and received it correctly. As of now forget about 256bit data now i am working with 32 bit data only. However, when attempting to send incremental data from the FPGA to the HPS, I encountered an issue. While the FPGA transmitted the incremental data as intended, the HPS consistently received constant value instead, which is an first value only. i am used a 32bit counter to send the incremental data, but it does not increments the counter. please find the below screenshots of my vhdl and c codes. with this code i am getting the incremental data from HPS to FPGA but not from FPGA to HPS

It looks like you posted a couple different versions of your C code. Which one are you running and what does the output look like? How are you verifying the FPGA is receiving data from the HPS? Are you using signal tap?

Thanks,
Greg

Hi,

Yes, I am verified in Signal Tap only. and as off now like, we are able to do read and write HPS to FPGA using LW_AVALON_MM interface. In case of read from HPS, avalon_slave_read signal is being high for two clock cycles. Where as avalon_slave_write is working fine, for each write it is being high for one clock cycle only. Why is to so, is there any setting to control that in AVALON_MM interface setting.

Please find the screenshot of the signal tap analyzer,

Hello,

I would look at the avalon memory mapped slave address in your signal tap. It's possible the hps is requesting a read from a different address for one of those two cycles. It's also possible two reads are queued up back to back if you are preforming multiple reads in your C code. I would also double check that you're using the correct clock for your counter that is associated with both the lw bus and mm slave.

Thanks,
Greg