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MKMitySOM Standard Carrier Board FMC pin assignment typo

Added by Maxim Kanevsky 5 days ago

Hello dear Sir/Madam,

I found some small typo in document: MitySOM-A5E-Standard-Development-Kit-Datasheet.pdf (inside document: 60-000098 Rev 1A):
- in table Table 17: J3 Connector Pin Assignments, pin C10 assigned to FPGA Pin: BR22
- in table Table 17: J3 Connector Pin Assignments, pin D12 assigned to FPGA Pin: BR22 (SAME!!!)
I've schecked in schematics of Carrier Board, these 2 nets are connected corrently on carrier board, so I guess, this is a typo in FPGA Pin. Can you please send me updated document or say what is the right connection??
Thanks,
Max


Replies (4)

MK RE: MitySOM Standard Carrier Board FMC pin assignment typo - Added by Maxim Kanevsky 5 days ago

In addition to previous message, pin H8 also doesn't seems to be right connection (VR31)

MF RE: MitySOM Standard Carrier Board FMC pin assignment typo - Added by Mike Fiorenza 5 days ago

Hi Max,

You are correct, it is a typo in the FPGA Pin column and not a board issue. Both nets route correctly on the carrier and on the SoM.

Your D12 row is the good one:

  • D12 (LA05_N), HVIO route: SoM pin J1-C12, HVIO_6A_12, FPGA pin BR22. Correct as printed.
  • C10 (LA06_P), HVIO route: SoM pin J1-F17, HVIO_6A_13, FPGA pin CH12. The datasheet incorrectly repeats BR22 here.

The error shifts the next row too, so I went through the whole table against the SoM schematic and the carrier schematic. Here is everything I found. In all of these the hardware is correct and only the document is wrong:

J13 Pin Signal Route Wrong column Doc says Should be
C10 LA06_P HVIO FPGA Pin BR22 CH12 (J1-F17, HVIO_6A_13)
C11 LA06_N HVIO FPGA Pin CH12 BU22 (J1-D13, HVIO_6A_14)
G15 LA12_P HVIO FPGA Pin BM22 BE29 (J1-E13, HVIO_6B_5)
G16 LA12_N HVIO FPGA Pin CF12 BE25 (J1-F13, HVIO_6B_6)
H8 LA02_N HVIO FPGA Pin VR31 BR31 (J1-F16, HVIO_6A_4)
G36 LA33_P HVIO SOM Pin J1-E18 J1-H26 (HVIO_6D_15, ball A35 is correct)
G37 LA33_N HVIO SOM Pin J1-E16 J1-H24 (HVIO_6D_16, ball A33 is correct)
D27 LA26_N HSIO SOM Pin J2-F06 J2-F04 (HSIO_2A_B4_N, ball BM89 is correct)

Two more in the Notes column, where the pin numbers are right but the net label is wrong:

  • D9 (LA01_CC_N, J2-C22 / CH59): should read HSIO_2A_T1_N, not HSIO_2A_T2_N.
  • H8 (LA02_N, J2-A22 / CH62): should read HSIO_2A_T2_N, not HSIO_2A_T2_P.

One other note, the FMC connector is J13, not J3. The caption in your Rev 1A copy says J3, which we have since corrected in Rev 1B on the website.

All of the pin errors above are still in our latest revision, so I do not have a corrected copy I can send you today. I am putting the corrections in now and will start our internal process to get that datasheet updated.

Let me know if you have any questions!

- Mike

MK RE: MitySOM Standard Carrier Board FMC pin assignment typo - Added by Maxim Kanevsky 5 days ago

Hello Mike, thank you so much for your help!!!
I'va attached my pin assignment table with fixes. Can you please take a look and see if exerything is correct. Meanwhile, I'll try to compile with these modifications.
Thanks,
Max

MF RE: MitySOM Standard Carrier Board FMC pin assignment typo - Added by Mike Fiorenza 5 days ago

Hi Max,

I reviewed your pinout and it looks correct to me.

One thing to mention is that I have posted our FMC example design and Wiki page here: A5E-FMC-Example. You obviously don't need to use this example design as you presumably already have a design in place, but the thing to note is the MitySOM development board has I/O Muxes for all of the User I/O going to the FMC connector. You'll want to make sure that these are configured correctly before trying to run any signals on the LA pairs. Details for doing so can be found on that page, particularly the Configuring the FMC user I/O muxes section. This uses our dev-kit device tree and an FMC overlay to enable software support for these Muxes. You can take a look at the device trees in our kernel source.

- Mike

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