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DCDSI panel integration on BSP 1.2: SDE panel node vs. upstream drm_panel — a few clarifying questions

Added by David Cuccia about 2 months ago

Hi Greg,

We're bringing our production display (Winstar W50DTYA3MNG10, 5" 720×1280, ILI9881C controller, MIPI DSI 2-lane video mode, plus a Goodix GT928 touch on I²C) to the MitySOM-QC6490 on BSP 1.2, and want to make sure we take the path you'd support.

From reading the layer, BSP 1.2's display is Qualcomm's downstream SDE stack ( msm_drm ), and your RPi 7" support in  mitysom-qc6490-devkit-rpi-panel.dtsi  describes the panel entirely in DT ( qcom,mdss-dsi-*  timings,  qcom,mdss-dsi-on-command , reset sequence, supply entries). We have an upstream-style  drm_panel  driver for the ILI9881C from our current CM5 product, but as far as "I" can tell (this is almost all tool-based help, perhaps obviously) nothing in the BSP 1.2 stack binds  drm_panel / mipi_dsi_device  drivers. So our plan is to generate an SDE panel node (init byte arrays + timings) from that driver's tables.

Questions:
  1. Can you confirm BSP 1.x consumes DSI panels only via  qcom,mdss-dsi-*  nodes — i.e., no  drm_panel  path under  msm_drm ?
  2. Have you brought up a DCS-initialized panel (as opposed to an external bridge like the RPi 7") on the devkit? If so, any conventions that mattered —  qcom,mdss-dsi-on-command-state  ( dsi_lp_mode  vs  dsi_hs_mode ),  qcom,mdss-dsi-lp11-init ,  qcom,mdss-dsi-init-delay-us , or the clock-lane handling for panels that want a non-continuous clock during init?
  3. On the devkit's DSI connector: which SoC/PMIC lines did you use for panel reset and backlight (PWM vs. enable), and which rails (1.8 V / 3.3 V) are available there? We'll mirror that on our adapter board.
  4. Direction check for BSP 2.0 (QLI 2.0): does it stay on downstream SDE or move to upstream  drm/msm  (where  drm_panel  would be the native path)? You mentioned DSI isn't working there yet — is that "not ported yet" or "stack changing"? This tells us which of the two descriptions is the long-lived one.

Thanks,
David


Replies (4)

GG RE: DSI panel integration on BSP 1.2: SDE panel node vs. upstream drm_panel — a few clarifying questions - Added by Gregory Gluszek about 1 month ago

Hi David,

Sorry about the delayed reply.

In response to your questions:

  1. This is the only methodology I'm currently aware of. I will update if I find something else.
  2. RPi 7" display is the only panel we have brought up on this platform so far. I will update as we add additional panels.
  3. For the adapter board we are using for the RPI 7": Pin 9 = RST. Pin 10 = PWM for backlight. Pin 11 = interrupt. Pin 12 = NC.
  4. I have not spent much time assessing the details of DSI in QLI 2.0. Once I am finished with the MIPI cameras on the QLI 2.0 effort I will work on this and let you know what I find.

Thanks,
Greg

GG RE: DSI panel integration on BSP 1.2: SDE panel node vs. upstream drm_panel — a few clarifying questions - Added by Gregory Gluszek 16 days ago

Hi David,

I just pushed commit 2a7b1d8dd56f4820cc4c649f1be8988742a57332 to branch wrynose-next in which integration for the Raspberry Pi 7" Display was added to QLI 2.0.

Please let me know if you have any questions.

Thanks,
Greg

DC RE: DSI panel integration on BSP 1.2: SDE panel node vs. upstream drm_panel — a few clarifying questions - Added by David Cuccia 15 days ago

Hi Greg,

Thanks for the QLI 2.0 DSI example. We're now planning adapter hardware for our own camera (ams Mira220, 2-lane CSI-2) and the Winstar DSI panel on the devkit, on the QLI 2.0 / upstream kernel path. A few electrical details would unblock us. If the devkit schematic sheets for J9-J13 and J15 can be shared, that alone would answer most of this.

CSI (J9-J13)

  1. What logic level are pins 17 (MCLK), 18 (IO), 20 (SCL) and 21 (SDA)? Are they straight to the SoC at 1.8 V, or is there level translation? Are there I2C pull-ups on the devkit, and to which rail? We want to connect an existing RPi-style camera adapter that may pull I2C up to 3.3 V.
  2. For each connector, which CCI/I2C bus, MCLK and SoC GPIO (for pin 18) does it use? The datasheet shows J13 using CSI3-SCL/SDA. Is that shared with J12, or a typo?
  3. Have you run the upstream qcom-camss driver (sc7280-camss) with any sensor on the devkit, or only the CamX stack? Is there any reason disabling the CamX nodes and enabling upstream camss in our own DT would not work on QLI 2.0?

DSI (J15)

  1. What is the logic level of DSI-IO0..DSI-IO2 (I/O expander outputs) and the touch I2C lines on J15? Which I2C bus and address is the expander on?
  2. What are the current limits for the 1V8-MIPI and 3V3-MIPI pins on J15?

No rush, and none of this is blocking today.

Thanks,
David

GG RE: DSI panel integration on BSP 1.2: SDE panel node vs. upstream drm_panel — a few clarifying questions - Added by Gregory Gluszek 13 days ago

Hi David,

The devkit schematics can be found here. Please let me know if you have any follow up questions after reviewing.

Regarding your question on qcom-camss vs CamX, we have only used the CamX stack thus far. I want to say I remember reading something regarding needing to build the qcom-multimedia-image instead of qcom-multimedia-proprietary-image if you want to use qcom-camss, but I cannot find the source (https://dragonwingdocs.qualcomm.com/archives/2.0/Technologies/Camera/camera-overview is what I quickly reviewed and might be worth a closer look).

Thanks,
Greg

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