Mity CPU Platforms » MitySOM-QC6490

Hi Greg,

We're bringing our production display (Winstar W50DTYA3MNG10, 5" 720×1280, ILI9881C controller, MIPI DSI 2-lane video mode, plus a Goodix GT928 touch on I²C) to the MitySOM-QC6490 on BSP 1.2, and want to make sure we take the path you'd support.

From reading the layer, BSP 1.2's display is Qualcomm's downstream SDE stack ( msm_drm ), and your RPi 7" support in  mitysom-qc6490-devkit-rpi-panel.dtsi  describes the panel entirely in DT ( qcom,mdss-dsi-*  timings,  qcom,mdss-dsi-on-command , reset sequence, supply entries). We have an upstream-style  drm_panel  driver for the ILI9881C from our current CM5 product, but as far as "I" can tell (this is almost all tool-based help, perhaps obviously) nothing in the BSP 1.2 stack binds  drm_panel / mipi_dsi_device  drivers. So our plan is to generate an SDE panel node (init byte arrays + timings) from that driver's tables.

1. Can you confirm BSP 1.x consumes DSI panels only via  qcom,mdss-dsi-*  nodes — i.e., no  drm_panel  path under  msm_drm ?
2. Have you brought up a DCS-initialized panel (as opposed to an external bridge like the RPi 7") on the devkit? If so, any conventions that mattered —  qcom,mdss-dsi-on-command-state  ( dsi_lp_mode  vs  dsi_hs_mode ),  qcom,mdss-dsi-lp11-init ,  qcom,mdss-dsi-init-delay-us , or the clock-lane handling for panels that want a non-continuous clock during init?
3. On the devkit's DSI connector: which SoC/PMIC lines did you use for panel reset and backlight (PWM vs. enable), and which rails (1.8 V / 3.3 V) are available there? We'll mirror that on our adapter board.
4. Direction check for BSP 2.0 (QLI 2.0): does it stay on downstream SDE or move to upstream  drm/msm  (where  drm_panel  would be the native path)? You mentioned DSI isn't working there yet — is that "not ported yet" or "stack changing"? This tells us which of the two descriptions is the long-lived one.

Thanks,
David