Building the provided FPGA project¶

Overview¶

The FPGA image that is provided on the virtual machine is given as a reference to how the FPGA can be used in unison with the HPS. The FPGA design heavily uses Qsys for connecting functional blocks together.

The image contains the following Qsys blocks:

• sysid_qsys - System ID Peripheral - This basic block is stores an 32 Bit system ID and the date the FPGA was built that can be read from the HPS
• hsmc_out_0 - PIO - This is a parallel I/O block that is connected to part of the full HSMC Connector
• hsmc_out_1 - PIO - This is a parallel I/O block that is connected to part of the full HSMC Connector
• hsmc_in_0 - PIO - This is a parallel I/O block that is connected to part of the full HSMC Connector
• hsmc_in_1 - PIO - This is a parallel I/O block that is connected to part of the full HSMC Connector
• fpga_ddr - DDR3 SDRAM Controller with UniPHY - This is the DDR controller for the DDR RAM that is attached to the FPGA, in the example it is then routed to the HPS so the HPS can access it from the HPS-to-FPGA AXI Bridge
• clk_100Mhz - Clock Source - Allows for inputting the CLK2DDR signal into the Qsys
• mm_clock_crossing_bridge - Avalon-MM Clock Crossing Bridge - Lets the HPS-to-FPGA bridge, running at 100Mhz, talk to the FPGA DDR Controller, running at 150Mhz

The project also uses the Altera Source and Probe block for controlling signals on the partial HSMC connector. The Altera Source and Probe is used for debug purposes and more info can be found here: http://www.altera.com/literature/hb/qts/qts_qii53021.pdf

Build Steps¶

The FPGA project can be located at:

	On the Virtual Machine	On the Support git Server
5CSX-H6-42A	/home/user/projects/mitysom_5csx_dev_board/dev_5csx_h6_42a	http://support.criticallink.com/gitweb/?p=mitysom-5cs/mitysom_5csx_dev_board.git;a=summary
5CSX-H6-4YA	/home/user/projects/mitysom_5csx_dev_board/dev_5csx_h6_4ya	http://support.criticallink.com/gitweb/?p=mitysom-5cs/mitysom_5csx_dev_board.git;a=summary
5CSX-H5-4YA	/home/user/projects/mitysom_5csx_dev_board/dev_5csx_h5_4ya	http://support.criticallink.com/gitweb/?p=mitysom-5cs/mitysom_5csx_dev_board.git;a=summary
5CSX-H6-53B	/home/user/projects/mitysom_5csx_dev_board/dev_5csx_h6_53b	http://support.criticallink.com/gitweb/?p=mitysom-5cs/mitysom_5csx_dev_board.git;a=summary
5CSE-L2-3Y8	/home/user/projects/mitysom_5cse_dev_board/dev_5cse_l2_3y8	http://support.criticallink.com/gitweb/?p=mitysom-5cs/mitysom_5cse_dev_board.git;a=summary
5CSE-H4-3YA	/home/user/projects/mitysom_5cse_dev_board/dev_5cse_h4_3ya	http://support.criticallink.com/gitweb/?p=mitysom-5cs/mitysom_5cse_dev_board.git;a=summary

The Quartus Project file is in each SOM-specific project folder and the top level vhdl and Qsys blocks can be found in vhdl. The Qsys blocks are pulled in as a git submodule so they can be reused more readily.

Steps:
If you are using the provided VM please skip to step 4

1. Clone our git repo of the project
   1. For the Dev Board with a MitySOM 5CSX-H6-42A
      

      git clone git://support.criticallink.com/home/git/mitysom-5cs/mitysom_5csx_dev_board.git
      

   2. For the Dev Board with a MitySOM 5CSE-L2-3Y8
      

      git clone git://support.criticallink.com/home/git/mitysom-5cs/mitysom_5cse_dev_board.git
      

2. Go into the newly created folder (pick the appropriate folder below for the MitySOM)
   1. MitySOM 5CSX
      

      cd mitysom_5csx_dev_board
      

   2. MitySOM 5CSE
      

      cd mitysom_5cse_dev_board
      

3. Initialize the git submodule for the Qsys IP
   

   git submodule init
   

4. Now update the submodules
   

   git submodule update
   

5. To make sure your project is up to date please pull down any changes from our git server
   

   git pull
   

6. Now open Quartus (there is a shortcut placed on the desktop)
7. Open the project in quartus File->Open Project and then navigate to and open
   1. MitySOM 5CSX: /home/user/projects/mitysom_5csx_dev_board/dev_5csx_h6_42a/dev_5csx_h6_42a.qpf
   2. MitySOM 5CSE: /home/user/projects/mitysom_5cse_dev_board/dev_5cse_l2_3y8/dev_5cse_l2_3y8.qpf
8. Now we will need to open Qsys in order to generate all the connecting logic between our function blocks Tools->Qsys
9. When Qsys opens it will prompt you to select a .qsys file for it open, pick dev_5csx_h6_42a.qsys or dev_5cse_l2_3y8.qsys that is available in the project folder
10. Once Qsys finishes opening the project, click Generate HDL in the bottom right and corner
11. Change Create HDL design files for synthesis to VHDL
12. Click Generate
13. Close Qys when its done
14. In Quartus make sure Flow in the Tasks window is set to Compilation
15. Now start the compilation Processing->Start Compilation
16. When finished there will be a .sof file in build/output_files. This file can be used to program the FPGA using a USB Blaster. If you would like to program the FPGA through linux please follow these steps: Programming the FPGA