Activity
From 09/10/2010 to 10/09/2010
10/01/2010
- JM 11:00 AM FPGA Development: RE: TLK100 Ethernet
- Mike,
FYI It was the bias resistor. There was a type in the BOM and a 49.9K was installed instead of a 4.99K. Once I replaced this everything worked fine.
John
09/27/2010
- JM 04:24 PM FPGA Development: RE: TLK100 Ethernet
- Mike
Just to be sure can you tell me how you pinned out the PCB footprint. Does it match this picture looking from the top or component side of the board?
John - JM 03:57 PM FPGA Development: RE: TLK100 Ethernet
Mike,
After talking this out with our software guy we are convinced its as your said,one of two things. The connection form the TLK100 to the Ethernet or a configuration pullup that configured it wrong on power up. The board does...- MW 03:49 PM FPGA Development: RE: TLK100 Ethernet
- Power up the unit in your board. Stop at u_boot and type:
- JM 02:05 PM FPGA Development: RE: TLK100 Ethernet
- The JTAG R's and connector are not installed.
I have the ethernet connected to my home switch.
I set the Ip address to a fixed value the was not used on my network, that is where the 172.15.1.37 came from. It is not that on... - MW 01:55 PM FPGA Development: RE: TLK100 Ethernet
- Hi John,
It looks like the OMAP MII interface is not making it to your network. The 169.254.X.X network means that the OMAP tried to use DHCP to get a network address, but was unable to find a DHCP server and get a response. After a... - JM 01:12 PM FPGA Development: RE: TLK100 Ethernet
- Here is the ip addrs when plugged into the Critial Link and IT WORKS
Critical Link dev IT WORKS
root@mityomapl138:~# ip addr show
1: lo: <LOOPBACK,UP,LOWER_UP> mtu 16436 qdisc noqueue
link/loopback 00:00:00:00:00:00 brd 00:00:00:... - JM 12:26 PM FPGA Development: RE: TLK100 Ethernet
- I didn't write them down I just typed them when he told me to. This was in u-boot. Once I typed them in I could ping in uboot I didn't get it to work yet in our control board but if I plug it into your development it works fine.
- MW 07:31 AM FPGA Development: RE: TLK100 Ethernet
- What were the software commands? If they involved setting the peripheral configuration in u-Boot, then they only need to be run once (assuming a "config save" was performed).
I guess I'm not sure I understand what you did to fix the ...
09/26/2010
- JM 11:13 PM FPGA Development: RE: TLK100 Ethernet
- Does the Ethernet on the MityDSP need to be initialized for each new TLK100 it gets plugged into? This one was initialized when plugged into one of the Critial Link boards and never reinitialized. When I first plugged it into the Cr...
09/25/2010
- MW 02:27 PM Software Development: RE: Clean Shutdown
- I think the most important thing is to mount the root filesystem and any filesystem you have your executable on with the noatime option, and then remount it as read only after the processor has booted. Ideally, the startup scripts from ...
09/24/2010
- JM 08:34 PM FPGA Development: RE: TLK100 Ethernet
- hey would it be possible that we talk on the phone?
858-254-0008
- MW 08:20 PM FPGA Development: RE: TLK100 Ethernet
- That message is OK. You can set up ethernet to use MII or RMII (but not both, and you're using MII).
It looks like it found the phy via MDIO OK and it is trying to get a dhcp address and failing.
You might try: - JM 08:06 PM FPGA Development: RE: TLK100 Ethernet
- I saw this among the test
EMAC: MII PHY configured, RMII PHY will not be functional
I attached the whole text - MW 07:50 PM FPGA Development: RE: TLK100 Ethernet
- Can you dump out the text from the boot sequence? Does the u-Boot locate the PHY (via the MDIO scan)?
-Mike
- JM 07:42 PM FPGA Development: RE: TLK100 Ethernet
- OK I made all the changes and it still does not work. I now think there are only two difference between out circuits:
1) pull up resistor values mine 4.75K and yours 2.2K
2) I grounded the Ethernet connector shield/cover and you ... - How do you recommend we handle shutdown of our embedded device in order to ensure the consistency of the Linux file system and anything else needed for a clean reboot?
We're doing a device that can be plugged in and unplugged at will.... - WF 12:02 PM Software Development: RE: LCD/Display questions
- We were able to get the LCD going with no problem, BTW. We'll be using it for our demo next week.
Thanks for the help.
09/23/2010
- MW 04:35 PM FPGA Development: RE: TLK100 Ethernet
- yes. you should add a pull-up.
- JM 04:16 PM FPGA Development: RE: TLK100 Ethernet
- Mike,
The green on the component means I used a different value cap or resistor. C216 is there but I used a 1uF ceramic Cap instead of the 0.1uF. I must have saw that in the TLK100 spec otherwise I would not have made it different. ... - MW 03:46 PM FPGA Development: RE: TLK100 Ethernet
- Hi John,
I think you need to tie the RESET line on the phy to the MII_RESET_N signal. The SYS_RESET_N does not get asserted in u-Boot (or the baseline kernel, as neither the SPI or audio device support has been tested and released ye... - JM 03:23 PM FPGA Development: RE: TLK100 Ethernet
- More information for you.
Attached is a comparison between the Critical link schematics and ours schematics. View this in a PDF reader and choose under menu View>Page display>Two Up to see full schematics.
The green shows the diff... - I know this is outside of your support area but I thought I would ask this in case you might have an idea of what to change or check. I appreciate any feedback your hardware guys can give me.
I used the same circuit for the Ethernet ...
09/22/2010
- MW 02:28 PM Software Development: RE: LCD/Display questions
- You'll need a different FPGA image. You also need to load an additional module (for the touchscreen controller on the LCD).
-Mike - WF 02:26 PM Software Development: RE: LCD/Display questions
- Yup. That did it.
For some reason, I had copied the instructions for the Rev. C board instead of the ones above.
Test gradient looks fine now, and so does my logo.
Now we move on to installing the LCD panel (the one we got from ... - MW 02:05 PM Software Development: RE: LCD/Display questions
- Ah. OK. You punched in the i2c commands for the Rev C board. You have 0x3f programmed into position 0x08.
Please use the following two commands (as described in the wiki): - TI 01:53 PM Software Development: RE: LCD/Display questions
- I added a simple test pattern generator to the wiki [[LCD_configuration]]. It draws a white box around the border of the frame buffer and fills it
with 16 bars. Each bar is one bit of color, so you should get 5 blue bars, 6 green bars,... - WF 01:50 PM Software Development: RE: LCD/Display questions
- Done. Here's what I see:
0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 4c 01 10 04 00 00 14 64 3f 06 80 00 a9 db 97 22 L???..?d???.???"
10: 00 00 00 00 00 22 e1 5f ac b2 5c 48 41 00 00 00 ....."?_... - MW 08:17 AM Software Development: RE: LCD/Display questions
- After you are up and running, could you please run a
09/21/2010
- WF 04:16 PM Software Development: RE: LCD/Display questions
- Definitely not a Rev C board, so it must be a B (I think we have an A here as well, but this isn't it).
Yes, actually, we do see a Linux prompt and cursor on that screen. Text is blue and the penguin at the upper left is blue and gree... - MW 03:22 PM Software Development: RE: LCD/Display questions
- Can you please confirm the revision of your board (B, or C)?
Before you write to the /dev/fb0 device, do you see a linux prompt? Is the text white (you may need to poke the blank variable as mentioned above). I am concerned about th... - WF 03:13 PM Software Development: RE: LCD/Display questions
- Got it working. A few oddities, but I'm now able to at least talk to the frame buffer.
The screen is all blue and green. Not sure why I don't get any reds. But I won't be using DVI for my real demo, so that's not very critical. Quite ... - TI 10:07 AM Software Development: RE: LCD/Display questions
- William
If you are seeing blue vertical stripes (every other pixel) then the frame buffer is working..
try the following command...
echo 0 > /sys/devices/platform/da8xx_lcdc.0/graphics/fb0/blank
If the screen shows a login prompt, th...
09/20/2010
- WF 10:53 PM Software Development: RE: LCD/Display questions
- OK -- we're definitely making progress here. I now see a raster on the DVI-based monitor. It's just vertical blue stripes, but clearly something is driving a signal out to the display. Yes, the instructions are involved, but they're easy...
- WF 09:37 PM Software Development: RE: LCD/Display questions
- Got it. I'll check this out right now and let you know what happens.
- MW 08:08 PM Software Development: RE: LCD/Display questions
- That's the right image. All the files show up at the bottom of the wiki.
I've updated the wiki with more instructions (they seem involved, but it's not that bad once you do it the first time), primarily with turning on the DVI cont... - WF 02:23 PM Software Development: RE: LCD/Display questions
- I downloaded the file "IndustrialIO_dvi_revA-B.bin" and used it to program the FPGA (in Linux, using the instructions from the Wiki). I then did the configuration commands found on the LCD configuration Wiki page. That seems to have gott...
- WF 11:56 AM Software Development: RE: LCD/Display questions
- We'll take a look at this setup today and let you know what happens.
The next thing we'll want to know is what commands (ioctl, for example) are enabled on the dev/fb device. I assume that the device will have various "files" visible ...
09/17/2010
- MW 06:32 PM Software Development: RE: LCD/Display questions
- It's off the [[Das_U-Boot_Port]] page from the start page. I'll look at making another entry.
- DV 06:06 PM Software Development: RE: LCD/Display questions
- Could you put the link to that wiki page into the wiki start page please.
- MW 05:52 PM Software Development: RE: LCD/Display questions
- The [[LCD configuration]] wiki page has been started that will cover the information you need. It's a work in progress, but there should be enough info in there now to at least force a frame buffer device into existence for the kernel.
- DO 02:27 PM FPGA Development: RE: How to implement bidirectional BLVDS in the FPGA (Spartan-6 )
- I received a reply back from Xilinx tech support.
They indicated that the approach for Spartan-6 would be similar to Virtex-E devices, and pointed me to an app note covering bidirectional BLVDS.
If anyone is interested, the app note ...
09/16/2010
- DV 08:26 PM Software Development: RE: LCD/Display questions
- I'll need a little more information about the uboot to be able to have it tell the kernel to initialize the device. Are we setting some environment variable here?
- MW 07:01 PM Software Development: RE: LCD/Display questions
- Mr. Schlunk,
The kernel included in the development kit provided should have the necessary code installed to support either the DVI interface or the LCD panel interface. To enable the display, the config options in uBoot must be upda... - We are trying to figure out how to get video out of the board and had a couple of questions.
Does your development kit already come with the settings file for the LCD that you sell, and for the DVI adapter? If not, can you tell me how... - I need to implement a data bus as part of an interface to the Xilinx FPGA, and it must be a bidirectional BLVDS interface. I looked in the Xilinx document: Spartan-6 FPGA SelectIO Resources, v1.3.
On p. 37, there is a diagram that descr...