Activity
From 02/24/2015 to 03/25/2015
03/25/2015
- 10:57 AM FPGA Development: RE: Mity L138F FPGA -> OMAP interrupt lines
- Hi Alex,
I was using MDK_2012-03-12 and in the included UCF the IO standard on those pin was different:
NET "o_... - I'm trying to get a new hardware design up and running with the MityDSP L138, using the Industrial IO board as a star...
03/23/2015
- 05:08 PM FPGA Development: RE: Mity L138F FPGA -> OMAP interrupt lines
- Chris,
Hopefully you happened upon this on your own but the details for the pin-configuration, voltage standards, ...
03/12/2015
- 11:06 AM FPGA Development: RE: FPGA serial programming interface
- We are happy to provide further assistance with this issue, however I will be contacting you directly at your e-mail ...
03/11/2015
- 10:23 AM FPGA Development: RE: FPGA serial programming interface
- Thanks for the information.
We are prototyping a future product and due to pin count restrictions we can't use par... - 10:18 AM FPGA Development: RE: FPGA serial programming interface
- I discussed this with one of our engineers here and it may be possible however they is likely a bit of work required ...
- 08:32 AM FPGA Development: RE: FPGA serial programming interface
- SB,
I apologize.
The M0 and M1 FPGA pins are tied to resistors on the module to GND (M0) and 3.3V (M1) forcing...
03/10/2015
- 05:04 PM FPGA Development: RE: FPGA serial programming interface
- I understand that. However, I would like to configure the FPGA in serial slave mode.
- 05:01 PM FPGA Development: RE: FPGA serial programming interface
- SB,
The FPGA is configured using 8 bit parallel slave select mode via the EMIFA bus connection to the Omap L138 pr... - hi,
are the pins CCLK, DIN and the MODE pins available on the OMAP-138 as GPIOs, or are they open/hardcoded on the...
03/05/2015
- 05:20 PM Software Development: RE: Write to SharedMem from DSP and read it from ARM
- Thanks for the cache info. Completely missed that part.
I reverted to the original code, and I've added BCACHE_wb(...
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