Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

03/26/2015

11:21 AM Software Development: RE: Pull-up Enable for MityDSP L138 (cp[0])

To be more specific, @CP[0]@ covers the following pins: @GP0[8] (OMAP_GP0_8), GP0[9] (OMAP_GP0_9), AHCLKX (AUDIO_SYS... Jonathan Cormier

03/25/2015

10:57 AM FPGA Development: RE: Mity L138F FPGA -> OMAP interrupt lines

Hi Alex,
I was using MDK_2012-03-12 and in the included UCF the IO standard on those pin was different:
NET "o_... Christopher Brunson

10:55 AM Software Development: Pull-up Enable for MityDSP L138 (cp[0])

I'm trying to get a new hardware design up and running with the MityDSP L138, using the Industrial IO board as a star... Ronald Kabler

03/23/2015

05:08 PM FPGA Development: RE: Mity L138F FPGA -> OMAP interrupt lines

Chris,
Hopefully you happened upon this on your own but the details for the pin-configuration, voltage standards, ... Alexander Block

03/12/2015

11:06 AM FPGA Development: RE: FPGA serial programming interface

We are happy to provide further assistance with this issue, however I will be contacting you directly at your e-mail ... Alexander Block

03/11/2015

10:23 AM FPGA Development: RE: FPGA serial programming interface

Thanks for the information.
We are prototyping a future product and due to pin count restrictions we can't use par... stephan berner

10:18 AM FPGA Development: RE: FPGA serial programming interface

I discussed this with one of our engineers here and it may be possible however they is likely a bit of work required ... Alexander Block

08:32 AM FPGA Development: RE: FPGA serial programming interface

SB,
I apologize.
The M0 and M1 FPGA pins are tied to resistors on the module to GND (M0) and 3.3V (M1) forcing... Alexander Block