Activity
From 04/26/2018 to 05/25/2018
05/23/2018
- AB 02:24 PM PCB Development: RE: New Design Bringup Question
- Thank you for the update! Happy to hear all is working now.
Alex - TR 03:55 AM PCB Development: RE: New Design Bringup Question
- Hi Alex, here's an update, checked for BOOTME and actually do see that output on the serial port, so the processor is alive.
However, after monitoring the SPI signals I realized an oversight on SW control of the level shifter for tri...
05/22/2018
- TR 11:12 PM PCB Development: RE: New Design Bringup Question
- Hi Alex, a few more details that may be helpful to know. The TI ADC eval board (we used before our board showed up) can be run from either a 3.3V or 5.0V rail. Since we were interfacing with the SPI signals directly from the MityDSP, it ...
- TR 09:06 PM PCB Development: RE: New Design Bringup Question
- Hi Alex, Thanks again... I'll be able to scope the SPI signals shortly.
So in our design we have an ADC with SPI signals at 5.0v so we level shift the MityDSP SPI signals beforehand. The 3.3v rail from the MityDSP is used as a Vcc fo... - AB 06:11 PM PCB Development: RE: New Design Bringup Question
- Tom,
Can you comment on J700 concerning the "where" used for +3.3V, SCLK, SIMO and SOMI? I see U901 mentioned for SCLK and SIMO but I'm guessing that's just a typo and it should be U902?
Thanks,
Alex - JC 05:47 PM PCB Development: RE: New Design Bringup Question
- Tom Riddle wrote:
> Hi Alex,
> ...
You should be able too, however perhaps something has gone wrong. Can you scope the SPI CLK, MISO, MOSI pins to see if they are stuck high or low during boot? - TR 05:34 PM PCB Development: RE: New Design Bringup Question
- Hi Alex,
Thanks, I will get a chance to check the boot sequence is a bit. Now I do not have anything on J700 Pin 29, but pins 11,13,15 are connected to an SPI DAC that we were hoping to use. I was expecting the SPI bus could be used ... - AB 04:48 PM PCB Development: RE: New Design Bringup Question
- Tom,
Sorry for the delay in getting back to you on this issue.
The first step you can take is to see if the MityDSP-L138F processor is working/alive. An easy test would be to power on the module with the serial port connected and t...
05/21/2018
- JC 03:56 PM FPGA Development: RE: FPGA GPIO issue
- Okay thanks Tom. I put that link in the wiki page to hopefully help people in the future.
05/17/2018
- Hi, we have an Industrial I/O board with a Mity-L138F SOM and are bringing up a custom HW design that plugs into it's expansion I/O connectors. We have successfully done development with two evaluation boards that we have interfaced with...
05/16/2018
- TR 03:15 PM FPGA Development: RE: FPGA GPIO issue
- Hi Jonathan,
Here's the link
https://support.criticallink.com/redmine/boards/12/topics/2224
It's been a few years since my last FPGA project, so I was a bit rusty. What I benefited from most was looking at that posted source ex... - JC 01:16 PM FPGA Development: RE: FPGA GPIO issue
- Can you link to the post? It may help me update the wiki page.
- TR 12:05 AM FPGA Development: RE: FPGA GPIO issue
- Hi Jonathan, thanks for the info... So I followed an example from a post a few years back (FPGA GPIO: toggle problem) and was able to get the GPIO going.
Regs, Tom
05/15/2018
- JC 03:23 PM FPGA Development: RE: FPGA GPIO issue
- The fpga can connect the gpio core to any pin you want. Gpio 144 should map to the first gpio core pin in the fpga image.
The .ucf file is used to map processor pins to net names in the vhdl.
MDK_2014-01-13/examples/industrial_io/... - Hi,
I am attempting to get some FPGA GPIO control going with an L138/LX45 IndustrialIO board. Have been following these instructions
https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Core_Device_Drivers
...