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New Design Bringup Question

Added by Tom Riddle over 3 years ago

Hi, we have an Industrial I/O board with a Mity-L138F SOM and are bringing up a custom HW design that plugs into it's expansion I/O connectors. We have successfully done development with two evaluation boards that we have interfaced with a number of the expansion I/O signals, so were comfortable with the MityDSP design details.

This new HW design lightly loads the +5V and +3.3V rails ie: J701 pins 37-40 & 41-44. Max current draw is 50ma on the 5v and 10ma on the 3.3. We brought up this design 1st with standalone +5, 3.3V power supplies without issues. We also then cabled over from the IndustrialIO expansion pins, just the power rails without issue. However when we engage the complete design to the expansion I/O the L138 will not boot. We still see the SOM's "Power Good" light come on but nothing more. Pressing Reset doesn't change this behavior. Removing our board sees the MityDSP resume normal boot.

With our board engaged, the voltage levels on the MityDSP +5v & +3.3v rails appear normal. Granted this design does utilize more pins ie: I2C, SPI pins from the MityDSP and FPGA GPIO but we successfully interfaced with these signals with our earlier evaluation board work.

Is there a suggested pin or SOM or IndustrialIO signal to monitor to know if we're getting thru power sequencing or with the boot process?

Thanks, Tom


Replies (8)

RE: New Design Bringup Question - Added by Alexander Block over 3 years ago

Tom,

Sorry for the delay in getting back to you on this issue.

The first step you can take is to see if the MityDSP-L138F processor is working/alive. An easy test would be to power on the module with the serial port connected and then hold the "Boot Me" button on the industrial IO. While holding the "boot me" button down press and release the "Reset" switch on the industrial IO board. You should then see the word "BOOTME" printed on the serial port each time you press the reset button while holding "boot me".

Second you mentioned that you are using some SPI pins from the expansion headers. The pins below interface with the SPI1 interface that has the on-SoM SPI NOR memory which is where UBoot is loaded from by default. Can you confirm if you have anything connected to Industrial IO board expansion header J700 Pin 29 (Module Pin 53)? Additionally do you have anything connected to J700 Pin 11, 13 and 15?

Thank you and hopefully we can resolve this quickly,

Alex

RE: New Design Bringup Question - Added by Tom Riddle over 3 years ago

Hi Alex,

Thanks, I will get a chance to check the boot sequence is a bit. Now I do not have anything on J700 Pin 29, but pins 11,13,15 are connected to an SPI DAC that we were hoping to use. I was expecting the SPI bus could be used as long at the CS was not conflicting. Please see the attached spreadsheet. If a pin says "open" it has no load to it.. yet. Regs, Tom

RE: New Design Bringup Question - Added by Jonathan Cormier over 3 years ago

Tom Riddle wrote:

Hi Alex,

Thanks, I will get a chance to check the boot sequence is a bit. Now I do not have anything on J700 Pin 29, but pins 11,13,15 are connected to an SPI DAC that we were hoping to use. I was expecting the SPI bus could be used as long at the CS was not conflicting. Please see the attached spreadsheet. If a pin says "open" it has no load to it.. yet. Regs, Tom

You should be able too, however perhaps something has gone wrong. Can you scope the SPI CLK, MISO, MOSI pins to see if they are stuck high or low during boot?

RE: New Design Bringup Question - Added by Alexander Block over 3 years ago

Tom,

Can you comment on J700 concerning the "where" used for +3.3V, SCLK, SIMO and SOMI? I see U901 mentioned for SCLK and SIMO but I'm guessing that's just a typo and it should be U902?

Thanks,

Alex

RE: New Design Bringup Question - Added by Tom Riddle over 3 years ago

Hi Alex, Thanks again... I'll be able to scope the SPI signals shortly.

So in our design we have an ADC with SPI signals at 5.0v so we level shift the MityDSP SPI signals beforehand. The 3.3v rail from the MityDSP is used as a Vcc for U902, a NC7SZ125 level translator for the MISO SPI. The other level translator U901 is used for SCLK and MOSI and use the +5.0V for it's Vcc.

All of the codec signals we have used with our TI eval board successfully. I also successfully used the SPI signals to the TI ADC eval board too. Regs, Tom

RE: New Design Bringup Question - Added by Tom Riddle over 3 years ago

Hi Alex, a few more details that may be helpful to know. The TI ADC eval board (we used before our board showed up) can be run from either a 3.3V or 5.0V rail. Since we were interfacing with the SPI signals directly from the MityDSP, it was powered off of the 3.3v rail so there was no need to translate levels. This didn't cause any problems during our initial SW development.

Tom

RE: New Design Bringup Question - Added by Tom Riddle over 3 years ago

Hi Alex, here's an update, checked for BOOTME and actually do see that output on the serial port, so the processor is alive.

However, after monitoring the SPI signals I realized an oversight on SW control of the level shifter for tri-stating MISO. After a change the board is booting fine now. Thanks for your input, it got me going in the right direction. Regs, Tom

RE: New Design Bringup Question - Added by Alexander Block over 3 years ago

Thank you for the update! Happy to hear all is working now.

Alex

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