Project

General

Profile

Converting FPGA Design from MityDSP to MityDSP-XM

This page describes the process of converting the VHDL for an FPGA design from targeting the MityDSP platform to compile the design for the MityDSP-XM.

Step 1 - Change Top level Entity Port Declarations

The MityDSP-XM uses a shift register to drive the LED and additional bank select bits on the larger flash. The shift register data/LED and clk signals use the pins that were previously direct connects. Comment out the o_fl_bank_sel_n and o_user_led_n ports and uncomment the o_sba_led and o_sba_clk ports.

MityDSP Ports:

      o_fl_bank_sel_n   : out std_logic;
      o_user_led_n      : out std_logic;
--      o_sba_led         : out std_logic;
--      o_sba_clk         : out std_logic;

MityDSP-XM Ports:

--      o_fl_bank_sel_n   : out std_logic;
--      o_user_led_n      : out std_logic;
       o_sba_led         :out std_logic; -- serial-bank-address data / user LED (FPGA_INIT_B/LED/SBA)
       o_sba_clk         :out std_logic; -- serial-bank-address clock

Step 2 - Add sba_ Signals

Place the following signal declarations with the other signals (before the "_begin_" keyword).

-- Bank select signals
signal t_sba_clk, sba_led : std_logic := '1';

Step 3 - Add sba_ Logic

Place the following logic near the end of the VHDL file replacing the old o_fl_bank_sel_n and o_user_led_n logic (old logic is commented out below).

------------------------------------------------------------------------------------
-- Top Level I/O Assignments
------------------------------------------------------------------------------------
--o_fl_bank_sel_n <= '0' when t_fl_bank_sel_n='1' else 'Z';
--o_user_led_n    <= not led_enable;

o_sba_led <= sba_led;
o_sba_clk <= 'Z' when t_sba_clk = '1' else '0';

Step 4 - Update the base_module Instantiation

Use the "MityDSP-XM" config; update the bank select ports.

------------------------------------------------------------------------------
-- Base Module
------------------------------------------------------------------------------
inst_base_module: base_module
   generic map(
      CONFIG => "MityDSP-XM" -- "MityDSP" | "MityDSP-XM" | "MityDSP-Pro" 
   )
   port map(
      emif_clk => emif_clk,
      .
      .
      .
--      i_bank_zero_clr => '0',
--      t_bank_sel_n => t_fl_bank_sel_n,
--      o_led_enable => led_enable
      o_sba_led => sba_led,
      t_sba_clk => t_sba_clk
   );

Step 5 - Update the Pin Assignments in the UCF Constraints File

Comment out the two MityDSP signals and uncomment the MityDSP-XM sba signals.

# MityDSP(Std) Flash Bank Select Connections
#NET "o_fl_bank_sel_n" LOC = "G2" | IOSTANDARD = LVCMOS33 ;
#NET "o_user_led_n"    LOC = "N9" | IOSTANDARD = LVCMOS33 ;

# MityDSP-XM Flash Bank Select Connections
NET "o_sba_clk"        LOC = "G2" | IOSTANDARD = LVCMOS33 ;
NET "o_sba_led"        LOC = "N9" | IOSTANDARD = LVCMOS33 ;

Go to top
Add picture from clipboard (Maximum size: 600 MB)