Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

11/07/2014

02:22 PM FPGA Development: RE: Modular SGDMA

Hi Jack,
We don't have any explicit examples of this but you will want to look into the userspace I/O driver. This... Daniel Vincelette

11/05/2014

01:40 PM FPGA Development: RE: Modular SGDMA

Hi Dan,
The issue seems to be with the polling. I brought out the empty signal to an oscilloscope and found that i... Anonymous

10/29/2014

10:58 AM Software Development: RE: Performance problem with baremetal code

In the meanwhile and after an ARM Cortex training I've found the root cause of the problem:
For enabling the cache... Christian Kempter

10/20/2014

04:34 PM FPGA Development: RE: Modular SGDMA

Hi Dan,
I polling the FIFO empty signal for the both the dispatcher and write master to ensure that only when both... Anonymous

10/17/2014

04:53 PM FPGA Development: RE: Modular SGDMA

Hi Jack,
You could try polling the dispatcher's busy bit instead but I'm not quite sure if that would solve your i... Daniel Vincelette

03:57 PM FPGA Development: Modular SGDMA

Hi
I'm running into a difficulty with the Modular SGDMA that is used in the HPS Memory example.
I have to send ... Anonymous