Modular SGDMA
Added by Anonymous about 10 years ago
Hi
I'm running into a difficulty with the Modular SGDMA that is used in the HPS Memory example.
I have to send dispatchers repeatedly in a infinite loop. I have it designed such that after I send the command to write the dispatcher, I wait until (on a white loop) I see both the FIFO for the dispatcher and the write master is empty and then I will proceed to the rest of my system and then back to writing the dispatcher.
However, I noticed that, in a rather random pattern, the system will just get stuck on the while loop waiting for the FIFO to be empty. The delay is rather random as well. Then after that the system continues on.
Any idea why there would be a delay for the FIFO in these systems to trigger the empty signal, especially when I only write my commands when they are empty.
Thanks,
Jack
Replies (4)
RE: Modular SGDMA - Added by Daniel Vincelette about 10 years ago
Hi Jack,
You could try polling the dispatcher's busy bit instead but I'm not quite sure if that would solve your issue. Any idea at how long the delay is for? Does the FIFO overflow because of it? Also you might want to put a bit of a sleep inside your infinite while loop just so the system doesn't lock up, if you haven't already.
Dan
RE: Modular SGDMA - Added by Anonymous about 10 years ago
Hi Dan,
I polling the FIFO empty signal for the both the dispatcher and write master to ensure that only when both FIFOs are empty when I will continue.
The delay varies, it's hard to predict.
Ideally we don't want to put any sleep there because we need the program to function. The code in between each time I call the write master is about 0.5 second. Does the write master and dispatcher not like to be flooded a stream requests?
Thanks,
Jack
RE: Modular SGDMA - Added by Anonymous about 10 years ago
Hi Dan,
The issue seems to be with the polling. I brought out the empty signal to an oscilloscope and found that it is on, but for some reason I'm not reading that on the software side.
I think it's better to switch to interrupt to deal with the issue. Do you have an example of doing interrupt?
I tried adding the interrupt files in Altera found in the "embedded\ip\altera\hps\altera_hps\hwlib\include", but ran into various issues.
Thanks,
Jack
RE: Modular SGDMA - Added by Daniel Vincelette about 10 years ago
Hi Jack,
We don't have any explicit examples of this but you will want to look into the userspace I/O driver. This should allow you to map in the FPGA interrrupts to a /dev/uio device.
I did a bit of searching and this looks like a good start: http://yurovsky.github.io/2014/10/10/linux-uio-gpio-interrupt/.
A quick example of a device tree entry for hooking up a UIO driver to FPGA IRQ 0 it would look something like:
uio0: uio0@20000000 {
compatible = "uio,irq";
interrupts = <0 40 4>;
};
40 is the FPGA 0 IRQ, gotten from here http://www.altera.com/literature/hb/cyclone-v/cv_54006.pdf#unique_42 and subtracted 32 from the value in the GIC Interrupt Number. The 4 means the interrupt will trigger when the line goes high.
Dan
