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Forum for FPGA developers

Subject Author Created Replies Last message
U-Boot Network Setup (MitySOM-5CSX-H6-42A) Jose Berlioz 01/10/2022 02:27 AM 4 Added by Jose Berlioz 6 days ago
RE: U-Boot Network Setup (MitySOM-5CSX-H6-42A)
U-boot Error Message Jose Berlioz 12/07/2021 09:27 PM 10 Added by Jose Berlioz 9 days ago
RE: U-boot Error Message
Using Signal Tap with the L2-3Y8 dev kit Travis Rawson 04/19/2021 10:17 PM 1 Added by Daniel Vincelette 9 months ago
RE: Using Signal Tap with the L2-3Y8 dev kit
Coldstart problem. Loading FPGA through Linux. Sergey Volkovoy 04/19/2021 03:09 PM 1 Added by Daniel Vincelette 9 months ago
RE: Coldstart problem. Loading FPGA through Linux.
HSMC Control Travis Rawson 02/17/2021 07:24 PM 2 Added by Travis Rawson 11 months ago
RE: HSMC Control
I2C Controller Harrison Barclay 07/11/2017 05:51 PM 3 Added by Evgeny Galyaev 11 months ago
RE: I2C Controller
Problem when programming FPGA from HPS Davide Vaccaro 03/19/2019 03:25 PM 9 Added by Vladislav Borchsh about 1 year ago
RE: Problem when programming FPGA from HPS
Quartus v20.1 errors building mitysom 5csx project Tristan Aldinger 09/09/2020 09:40 PM 2 Added by Alexander Block over 1 year ago
RE: Quartus v20.1 errors building mitysom 5csx project
Quartus Device id for mitySOM 5CSE-H4-3YA-RI-ND Pablo Camacho 09/02/2020 09:30 PM 1 Added by Daniel Vincelette over 1 year ago
RE: Quartus Device id for mitySOM 5CSE-H4-3YA-RI-ND
mitySom 5csx and opencl 19.1 Matthieu Moretti 06/17/2020 09:04 AM 0
FPGA programming problems Dario Russo 05/17/2020 07:17 AM 11 Added by Dario Russo over 1 year ago
RE: FPGA programming problems
MitySOM-5CSX-H6-42A files generation issues Dario Russo 02/07/2020 05:55 PM 2 Added by Dario Russo almost 2 years ago
RE: MitySOM-5CSX-H6-42A files generation issues
Set timing constraints Davide Vaccaro 07/03/2019 09:20 AM 1 Added by Michael Williamson over 2 years ago
RE: Set timing constraints
FPGA programming Davide Vaccaro 04/29/2019 03:43 PM 2 Added by Davide Vaccaro over 2 years ago
RE: FPGA programming
Load FPGA from Linux to MitySOM-5CSX-H6-4YA Mathew Jones 11/02/2017 04:12 PM 2 Added by Mathew Jones about 4 years ago
RE: Load FPGA from Linux to MitySOM-5CSX-H6-4YA
Power fail interrup Clyde Shappee 06/20/2017 02:05 PM 3 Added by Alexander Block over 4 years ago
RE: Power fail interrup
CLK2DDR signal on development board franco spinella 02/02/2017 11:47 AM 1 Added by Adam Dziedzic almost 5 years ago
RE: CLK2DDR signal on development board
HDMI Output splash screen is intermittently displayed on boot Stephen Snyder 08/09/2016 09:43 AM 29 Added by Stephen Snyder over 5 years ago
RE: HDMI Output splash screen is intermittently displayed...
5CSX-H6-53B-RC with PCIe Hard IP (Root) Thomas Carpenter 07/09/2016 10:22 PM 4 Added by Adam Dziedzic over 5 years ago
RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)
HDMI Output and Quartus Versions Stephen Snyder 06/20/2016 11:07 AM 1 Added by Alexander Block over 5 years ago
RE: HDMI Output and Quartus Versions
LVDS transceiver for 1000Mb Ethernet MAC & 1000Base-X problem Charles Garcia 01/12/2016 11:08 AM 1 Added by Adam Dziedzic about 6 years ago
RE: LVDS transceiver for 1000Mb Ethernet MAC & 1000Base-X...
JTAG: No JTAG hardware available Darius Bethel 11/10/2015 11:42 AM 3 Added by Adam Dziedzic about 6 years ago
RE: JTAG: No JTAG hardware available
HSMC1 in MityARM-5CSX Baseboard Alejandro Concepci├│n 09/30/2015 05:56 AM 0
HSMC1 pinout Florian Rieger 05/26/2015 03:54 AM 2 Added by Florian Rieger over 6 years ago
RE: HSMC1 pinout
Example project Malcolm Hartnell 04/09/2015 08:20 AM 1 Added by Michael Williamson almost 7 years ago
RE: Example project
Load FPGA from uboot Anonymous 01/05/2015 03:28 PM 3 Added by Daniel Vincelette about 7 years ago
RE: Load FPGA from uboot
100MHz Input clock (CLK2 - DDR3) Issue Alexander Block 12/11/2014 07:50 PM 0
Writing to HPS memory Vidya Govindan 11/25/2014 07:39 AM 1 Added by Michael Williamson about 7 years ago
RE: Writing to HPS memory
Modular SGDMA Anonymous 10/17/2014 03:57 PM 4 Added by Daniel Vincelette about 7 years ago
RE: Modular SGDMA
HPS Memory Controller Anonymous 11/20/2013 06:25 PM 34 Added by Anonymous over 7 years ago
RE: HPS Memory Controller
Load FPGA Timeout Error Anonymous 01/20/2014 05:19 PM 21 Added by Alexander Block over 7 years ago
RE: Load FPGA Timeout Error
FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR) Nigel Doe 07/23/2014 01:27 PM 3 Added by Adam Dziedzic over 7 years ago
RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)
How to access FPGA internal memory through AXI slave interface protocol Bill Lee 06/25/2014 10:43 PM 10 Added by Adam Dziedzic over 7 years ago
RE: How to access FPGA internal memory through AXI slave ...
Time limited SOF file question Rich Bagdazian 03/21/2014 02:04 PM 3 Added by Rich Bagdazian almost 8 years ago
RE: Time limited SOF file question
Signal Tap & JTAG FPGA Programming Anonymous 02/13/2014 12:58 PM 3 Added by Daniel Vincelette almost 8 years ago
RE: Signal Tap & JTAG FPGA Programming
Ethernet Anonymous 11/19/2013 05:49 PM 4 Added by Gregory Gluszek almost 8 years ago
RE: Ethernet
I/O voltage Nigel Doe 12/23/2013 08:15 AM 5 Added by Nigel Doe about 8 years ago
RE: I/O voltage
HSMC to GPIO Anonymous 12/06/2013 03:00 PM 1 Added by Daniel Vincelette about 8 years ago
RE: HSMC to GPIO
FPG DDR3 Memory Pin Assignment Anonymous 11/28/2013 04:57 PM 8 Added by Anonymous about 8 years ago
RE: FPG DDR3 Memory Pin Assignment
Link Down Anonymous 11/20/2013 04:53 PM 2 Added by Anonymous about 8 years ago
RE: Link Down
Quartus II Subscription Edition Error Anonymous 11/20/2013 03:51 PM 5 Added by Gregory Gluszek about 8 years ago
RE: Quartus II Subscription Edition Error
Clock Anonymous 11/19/2013 05:18 PM 1 Added by Michael Williamson about 8 years ago
RE: Clock
Unable to access Linux Anonymous 11/18/2013 04:38 PM 1 Added by Michael Williamson about 8 years ago
RE: Unable to access Linux
Input/Output interfacing Rich Bagdazian 11/12/2013 04:47 PM 6 Added by Michael Williamson about 8 years ago
RE: Input/Output interfacing
FPGA - HPS DDR Memory Anonymous 11/18/2013 04:42 PM 1 Added by Michael Williamson about 8 years ago
RE: FPGA - HPS DDR Memory
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