HSMC1 pinout
Added by Florian Rieger almost 9 years ago
Hi,
I am using the mityarm_5csx_dev_board_hsmc_setup.tcl to define the pinout of the HSMC1 interface of my FPGA design, and found a discrepancy in the documentation. Based on the schematic, I assume the signals HSMC1_SMSDA/HSMC1_SMSCL need to be interchanged in mityarm_5csx_dev_board_hsmc_setup.tcl. The MitySOM-5CSX Development Kit seems to be wrong on the documentation of the HSMC1_SMSCL signal too (BTW - HSMC1_CLKIN0, HSMC1_TX9_P and HSMC1_TX9_N are associated to a bank 3B instead of 4A).
The attached spreadsheet merges the information found in the documentation and shows the discrepancy. I suppose hat the HSMC1 pins 33 (HSMC1_SMSDA) and 34 (HSMC1_SMSCL) are connected to the FPGA pins AF28 and AF27 respectively, can you validate this assumption?
For my design, I would also like to reuse/reassign some output signals as inputs for the FPGA (i.e. HSMC1_SMSCL, HSMC1_PRSNTn, HSMC1_CLKOUT0), are there any limitations from the base board that I must consider if I flip the direction of these pins (except that my HSMC daughter card must reflect those changes)?
Thanks,
Florian
Replies (2)
RE: HSMC1 pinout - Added by Alexander Block almost 9 years ago
Floria,
A) We confirmed that the .tcl script is in fact incorrect for that pin-assignment.
Correct pin assignment (as you noted):
set_location_assignment PIN_AF27 -to HSMC1_SMSCL set_location_assignment PIN_AF28 -to HSMC1_SMSDA
Note that we have more up to date examples and .tcl scripts in our example project GIT repos however the SCL/SDA pin swap is still present, but will be addressed in the next release/update.
| On the Virtual Machine | On the Support git Server | |
| 5CSX Base | /home/user/mitysom_5csx_dev_board/base_project | http://support.criticallink.com/gitweb/?p=mitysom-5cs/mitysom_5csx_dev_board.git;a=summary |
| 5CSE Expanded IO | /home/user/mitysom_5cse_dev_board/dev_exp_5cse_l2_3y8_base | http://support.criticallink.com/gitweb/?p=mitysom-5cs/mitysom_5cse_dev_board.git;a=summary |
B) Concerning the datasheet discrepancy it has HSMC1_SMSDA and HSMC1_SMSCL mapped to the proper HSMC pins however the SoM pin column is incorrect for these pins. HSMC1_SMSDA should be SoM pin 52 and HSMC1_SMSCL should be SoM pin 54. You are correct on the bank voltage 3B vs 4A discrepancies.
We have created action items for these discrepancies (the datasheet ones were already noted just not published yet unfortunately) and will get them addressed.
C) Concerning the direction change for the HSMC1 pins mentioned if your usage for them is low speed then that should be fine however if you are trying to do high speed, I.E. use the HSMC1_CLKOUT0 as a CLK input, you may run into issues. If you have further concerns about this please let us know what specific use case you have planned for each pin and we can provide some feedback and/or recommendations.
Thanks,
Alex
RE: HSMC1 pinout - Added by Florian Rieger almost 9 years ago
Alex,
thank you for clearing that up!
B) Just for the record, SMC1_SMSDA should be SoM pin 54 and HSMC1_SMSCL should be SoM pin 52.
C) Yes, the usage of those pins is quasi-static, they form part of a 9 bit configuration interface. Since you have offered your feedback/recommendations, I attached the pinout of the HSMC1 interface as I intend to use it. I'd be glad to hear your opinion on that.
Thanks,
Florian
