FPGA - HPS DDR Memory
Added by Anonymous about 11 years ago
Hi,
I need to design system where I store input data to the memory via the FPGA, and then export it out to my computer through the HPS.
My only problem is that I am not very familiar with using the AXI bridge. Can someone please provide some help or examples on how to write to the HPS memory from the FPGA side. Is there any documentation on the HPS memory controller (specifically I need the timing diagrams)?
Cheers!
Jack
Replies (1)
RE: FPGA - HPS DDR Memory - Added by Michael Williamson about 11 years ago
Hi Jack,
I would recommend using Qsys and exporting the FPGA->HPS DDRAM bridges. Then if you create an Avalon memory mapped controller (spec including the timing diagrams can be found here), you can write FPGA code to initiate a transfer. Avalon sits on top of the AXI interfaces. Qsys will translate the Avalon bus to the AXI controls for you. Avalon is a much simpler bus than the full AXI interface, which you can download from ARM Holdings to get the detailed timing diagrams.
We have been using the Scatter Gather DMA controller from Altera to allow software to push data in and out of the FPGA to streaming and/or memory mapped interfaces, which is pretty easy once you get the flow of Qsys and the Avalon framework.
I will try to post a couple of examples, but right now they are pretty specific to projects we are working on...
-Mike
