Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

Jack,

We do not currently have an example that uses a non-packetized Avalon stream. There should be an option in the SGDMA controller to disable packets but we haven't tried to use it.

Dan

Hi Dan,

Regarding the SGDMA Write Master Core. I looked through the document for this core and it doesn't give any information on these questions.

For the write command sink port, what exactly is the purpose of "write stride" (91-76 bits)?

If the stride width goes from 1 to 16, how can I use the fixed address which would require me to set it to 0?

Right now I'm thinking of using the write master directly in the VHDL.

Thanks!

Jack

Hi Jack,

Looking in the SGDMA dispatcher core user guide, it appears that if you use the extended descriptors you can set the write stride to zero, which would allow you to continuous write to the same address.

What is your required bandwidth? It might be simpler to use the HPS to FPGA bridge and have the HPS poll this register if this isn't a ultra high speed application.

Dan

Hi Dan,

Our data is coming in at about 40 MHz,

Jack

Also, I'm trying to by pass the SGDMA dispatcher and use the write master directly.

Jack

At that rate it might be simpler to create a FIFO in the FPGA and connect it to the light weight HPS to FPGA bridge. Then have the HPS poll that register continuously. We've run that interface at 100Mhz, mainly for control and status registers. The bus can be configured to be 32, 64, or 128 bits wide.

Dan

Hi Dan,

Don't you mean connect it to the FPGA to HPS AXI bridge?

Our input data is processed in the FPGA.

Thanks!

Jack

Nope, if you connect it to the HPS to FPGA bridge you can treat it more like a register that the code on the HPS reads. You could also use the FPGA to HPS bridge to write to a specific location in memory, though I have no experience with this bridge.

Dan

Hi,

Just raising this subject again. I'm going through the document for the sgdma_dispatcher, but do you guys have an example where you check to see if the dispatcher has finished transferring?

I tried reading the CSR Status register but not sure which one would precisely do the job. If it's the IRQ, don't I need a ISR to deal with that, if so do you have any examples of this or can I just poll it?

Thanks,

Jack