Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

A customer has the 100MHz DDR3 clock being fed into the module through Pins 117 and 119 on a custom carrier board and is using it to clock some ADC data. However after a little run-time it stops working as noted below:

I'm having a really weird problem with the DDR3 100Mhz clock. I included this in my design from your eval board, however I am not 
using it as a clock for the FPGA RAM. I'm using it to clock out two ADC clocks.  That aspect of the design works fine. Its when I use the 
clock internally that I run into problems. 

Case in point: I have a logic block that uses this clock as a count down to initiate a burst of a FIFO-full of ADC input data. With this clock, 
I set a timer to fill the buffer full of data every 5 seconds. The frustrating part of this is that it WORKS for about 10-15 fifo-fuls of data but then 
it stops.  As best I can tell, the millisecond strobe I use based off this clock stops being registered by the logic so it sits in the idle stage. 

When I used the 100Mhz HPS user 0 clock instead, it works like a charm. 

The DDR3Clock goes through an altera_pll block  with a multiplier of 1 so it just basically goes through. 

Any idea how I can get this to work?