CLK2DDR signal on development board
Added by franco spinella about 7 years ago
Hi, I'm designing my own carrier card, but I've some doubts about the use of the bank 4A.
I need to connect the the mitysom module some parallel DACs with 3.3 volts single ended levels as outputs.
I need about 34 pins so I was planning to use the bank 4A, but:
- In the demo board the VCCIO-4A is connected to 2.5 volts.
- In the demo board design the CLK2DDR_P and CLK2DDR_N signals are connected to the bank 4A and comes from a SiT9120-2C3 100 MHz differential oscillator with LVDS levels, in the demo firmware design
it is defined only the pin Y13, connected to CLK2DDR_P and is defined as SSTL-135.
If I try to define all the 4A pins eccept Y13 as LVTTL3.3 the demo design does not compile, because of the presence of the SSTL-135 clk signal.
Here are my doubts:
1) I could be wrong but from the datasheet it seems that the STTL-135 signals needs a 1.35 v VCCIO, so I can't understand why it is compiling with all the other pins defined with a 2.5 v level ...
2) The SiT9120 has a lvds differential output, while in the demo firmware the Y13 pin is defined as single ended SSTL-135. How can it work ?
3) In my custom carrier card can I connect the clock for the DDR to another bank and leave the 4A empty so that I could connect the VCCIO4A to 3.3 volts and define all the bank pins as 3.3v lvttl ?
4) Does this clock has to come from a diffrential oscillator to garantee a correct operation for the DDR3 ?
Sorry if I was too long but I'm finalizing my card design and I would like to be sure that I don't do mistakes with the DDR ...
Thanks
Franco
Replies (1)
RE: CLK2DDR signal on development board - Added by Adam Dziedzic about 7 years ago
Hello Franco,
Thanks for checking before committing to the board... The I/O standard does indeed sound like a mismatch!
The likely difference between the 2.5V I/O design building and a failing 3.3V I/O design is due to the (VPD) PreDriver voltage. This is handled internal to the MitySOM for each flexible Bank where an I/O voltage is supplied from the baseboard. With 2.5V I/O rails and lower, the PreDriver voltage fed to that bank is at 2.5V. When running a bank voltage higher than 2.5V, the predriver voltage matches the VIO voltage. The FPGA supports multiple voltage standards on inputs and the list of supported standards depends on a number of factors including the VPD. Note that Banks 3B and 4A share the same VPD and therefore, must both run the same VIO voltage when using 3.3V VIO for either bank.
1) To drive an output, yes - multiple input standards can be supported together, but there are very specific rules.
2) Possibly the LVDS thresholds are sufficient in this case to meet the SSTL135 input levels. There is likely a better approach.
3) For clarity, this clock input is only used to meet the timing requirements on the FPGA-DDR, not the HPS-DDR. The Quartus tools have advanced since the initial MitySOM design, so it is not completely ruled out. When defining the module, the task was monumental to meet the timing requirements for the FPGA DDR, without consuming the Bank4A/3B I/O pins (where most of the IOs are located). The one clock input that would meet the requirement was the Bank4A clock input, specifically the _P side that has a direct connection to the corner PLL.
4) You can change the clock input to a 3.3V source - this should be OK, but make sure the single-ended input is on the _P side of the clock input.
Please let us know if you would like a schematic review before finalizing your design. It benefits us both to have successful designs.
Thanks,
Adam
