Using Signal Tap with the L2-3Y8 dev kit
Added by Travis Rawson over 3 years ago
Hello,
I am trying to get Signal Tap working on the my system, but I keep running into failures. I am able to connect a usb-blaster device to the JTAG pins on the white connector. I am also able to find the hardware (usb-blaster) and the device (@1: 5CSE(BA2|MA2)/5CSXFC2C6) inside of Signal Tap. Whenever I go to download the sof onto the board, the FPGA seems like it gets reprogrammed only when I stop the dev board from fully booting. Even when it seems like it programs correctly, Signal Tap always comes back with an error of some kind.
My questions are:
1) Is there some state I need to put the dev board in to work with Signal Tap, or letting it fully boot is fine?
2) Are there some setting I need to do in Signal Tap to make it work with the Cyclone V/MitySOM dev board, or do I need to seek out some other source to help with the Signal Tap errors?
Thanks for all the help so far!
Replies (1)
RE: Using Signal Tap with the L2-3Y8 dev kit - Added by Daniel Vincelette over 3 years ago
Hi Travis,
I'm sorry for the long delay, are still seeing issues with SignalTap? My normal flow for SignalTap debug especially if the HPS is accessing cores on the bridges is to convert my SOF to a RBF and have u-boot program it on boot. After that I then signal tap connect instead of using it to program the FPGA.
Also please note that we have found an issue with some JTAG pods reseting the HPS on connection. In order to fix this problem you might need to cut off one of the pins on the JTAG adapter board that we supply with the dev kit. For more information on that please take a look at the following wiki: https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Module_Debug_Connection#JTAG-Only-Adapter-80-000616
Best regards,
Dan
