FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR)
Added by Nigel Doe over 10 years ago
Although your reference design using FPGA DDR compiles as supplied, when I select the correct device (5CSXFC6C6U23C8ES) for my hardware I get timing violations on the FPGA DDR that I have been unable to fix.
I cannot create extra margin as I cannot lower the DDR clock below the 300MHz minimum and I cannot implement using the hard memory controller as the pin selection is not suitable.
Any suggestions on how to overcome this?
Nigel.
Replies (3)
RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR) - Added by Adam Dziedzic over 10 years ago
Hi Nigel,
You are correct, the C8ES devices do not meet timing with the FPGA DDR according to Quartus. The ES silicon was not qualified to any faster speed grades than C8, though it does work according to our tests. We designed the SOM targeting the C7 speed grade devices and there is some margin with those devices. The C8ES modules are intended for evaluating the product and getting started on a design. The production devices have been built up and will provide more margin that is qualified by the Quartus build tools and device qualification. According to our internal test results, there is some margin on the FPGA DDR interface with the C8ES devices, though we have not quantified it.
There are two approaches to getting a Quartus build.
- You can run the build with the C8ES target device and ignore the timing violations for the FPGA DDR interface.
- Alternatively, the Quartus project could target the C7 device and assume the C8ES will meet timing of a C7.
Neither path is perfect, but we have used both with success.
One other comment... The FPGA DDR interface has the address and data buses split across two sides of the device. Because of this, the fractional PLL used is important and should match the example. The clock input is also called out in the schematic to have the proper clock input with a dedicated path feeding the fPLL needed by the FPGA DDR interface.
If you do Not need the bandwidth available, it is possible to run the DDR slower. Micron has some app notes covering the changes required to run the DDR3 memory at a slower clock speed. These are, in general, more refresh cycles to keep the memory cells active. With the slower clock speed, the time between refresh commands is maintained by calling refresh commands after fewer clock cycles.
Thanks,
Adam
RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR) - Added by Nigel Doe over 10 years ago
Hi Adam,
Thanks for the insights.
Do you know how to persuade qsys to run the DDR at a slower speed? In normal use it will not allow anything less than 300MHz.
Thanks,
Nigel.
RE: FPGA DDR3 on 5CSX-H6-42A-RC-X (DDR) - Added by Adam Dziedzic over 10 years ago
Hi Nigel,
I don't believe there is a way to do it directly in QSYS. You may be able to patch your generated outputs to get over that hurdle. As you would expect, Altera has the normal minimum frequency requirement programmed in so users avoid the memory cells fading early due to longer clock cycles. If this is a need for your project and you would like some additional help, we could open a project contract to help get through the requirement. The simplest and most cost effective solution would be to run at 300MHz.
- Adam
