Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

03/27/2019

09:53 AM FPGA Development: RE: Problem when programming FPGA from HPS

I attach the simple block diagram-based Quartus project that takes in input a 100 MHz differential clock and outputs ... Davide Vaccaro

03/26/2019

05:23 PM FPGA Development: RE: Problem when programming FPGA from HPS

Can attach a copy of your reference project? Is it based off of the one on our support site?
-Mike Michael Williamson

04:55 PM FPGA Development: RE: Problem when programming FPGA from HPS

So, I tried all the methods listed in https://rocketboards.org/foswiki/view/Documentation/GSRD131ProgrammingFPGA, but... Davide Vaccaro

03/25/2019

03:11 PM FPGA Development: RE: Problem when programming FPGA from HPS

Hi Mike,
in the "final" Quartus program I will indeed need to change the configurations you mentioned, but for a s... Davide Vaccaro