Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

05/25/2020

08:39 AM FPGA Development: RE: FPGA programming problems

Hi Dan,
thank you very much for helping me with this problem.
Attacched you can find the boot logs for the three ca... Dario Russo

05/22/2020

05:08 PM FPGA Development: RE: FPGA programming problems

Hi Dario,
Thank you for the bootlog and answering my questions.
If you are seeing the yellow led toggle in u-bo... Daniel Vincelette

07:59 AM FPGA Development: RE: FPGA programming problems

Hi Dan,
yes, I still have the multiple boots problem.
1) I'm not changing the SDRAM bridge configuration between bu... Dario Russo

05/21/2020

01:01 PM FPGA Development: RE: FPGA programming problems

Hi Dario,
If you are still seeing it take multiple boots to load the "new" rbf from u-boot then it shouldn't be a ... Daniel Vincelette

08:18 AM FPGA Development: RE: FPGA programming problems

I checked the preloader and uboot and are updated. I noticed that in the bootlog the bridges are not initialized:
... Dario Russo

05/17/2020

07:07 PM FPGA Development: RE: FPGA programming problems

Hi Mike,
thank you for the detailed answer. I don’t used interruputs and UART or SPI, but I use the sdram bridge. Th... Dario Russo

11:44 AM FPGA Development: RE: FPGA programming problems

Hi Dario,
In your FPGA project, did you modify any of the HPS peripheral settings over your standard load? For ex... Michael Williamson

07:17 AM FPGA Development: FPGA programming problems

Hi,
I’m working with MitySOM-5CSX-H6-42A development kit and I would like to solve some annoying problems. After gen... Dario Russo