Activity
From 03/05/2022 to 04/03/2022
03/31/2022
- DV 11:31 AM Software Development: RE: MitySOM 5CSX-H6-53B-RC not booting
- Hi Franz,
One difference that stands out to me is the INPUT/OUTPUT TERMINATIONs used. Because the SOM uses a different RZQ value than the defaults that quartus use please change the HPS DDR INPUT_TERMINATION/OUTPUT_TERMINATION for the... - FS 02:23 AM Software Development: RE: MitySOM 5CSX-H6-53B-RC not booting
- Hello Dan,
I have attached the .qsys and .qsf files. These have the instances added as well as the row address width set to 16 so I'm not sure what other change is needed, maybe the clock needs to be changed for the 53B-RC?
Thanks,...
03/27/2022
- DV 06:14 PM Software Development: RE: MitySOM 5CSX-H6-53B-RC not booting
- Hi Franz,
For the issue with the 53B SOM hanging at "Initializing SDRAM ECC" the device tree doesn't come into play, at this point the SOM would only care about the preloader. From a highlevel your soc_sys.dts looks ok.
Dan
03/25/2022
- FS 09:42 PM Software Development: RE: MitySOM 5CSX-H6-53B-RC not booting
- Hello Dan,
I did already have those instances added to my .qsf. Before I share my .qsys and .qsf files I would like to verify if my device tree files had the correct changes, I have attached all the ones being used here. The changes b...
03/21/2022
- DV 12:02 PM Software Development: RE: MitySOM 5CSX-H6-53B-RC not booting
- Hi Franz,
I don't believe changing the pin mux like you have would cause the preloader to hang at initializing the DDR, this normally occurs if the row width wasn't adjusted to account for the extra size. Also you are right the row ad...
03/16/2022
- DV 08:21 PM FPGA Development: RE: Differences in 5CSE-L2-3Y8-RC production runs?
- Hi Lucas,
That is an interesting finding, I'm not aware of any reports of lot to lot clock instabilities. Are you passing the HPS user clock to the FPGA as your main clock source for your FPGA design or is your FPGA being clocked by a... - Hello. We've been doing some troubleshooting on prototype units that use the 5CSE-L2-3Y8-RC for DSP on the FPGA end and further treatment on the ARM CPU side and were puzzled by two units with fairly similar behavior on the analog front ...
- FS 05:39 AM Software Development: RE: MitySOM 5CSX-H6-53B-RC not booting
- Hello Dan,
Unfortunately, the boot still stalls with SDRAM_SCRUBBING enabled. As for the HPS instance, the only differences are the added FPGA to HPS interface and a few different peripheral pins which are an added SPIM0 pin and no QS...
03/09/2022
- DV 12:12 PM Software Development: RE: MitySOM 5CSX-H6-53B-RC not booting
- Hi Franz,
This hang might be due to not enabling SDRAM_SCRUBBING in the bsp-editor, as described in our bootloader build instructions step 9 (https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_uboot_181)
I ... - FS 03:30 AM Software Development: RE: MitySOM 5CSX-H6-53B-RC not booting
- Hello Dan,
I have changed the hps row address width from 15 to 16 for the MitySOM 5CSX-H6-53B-RC and added package skew compensation, IO standard and output termination lines for the extra hps address in the qsf file which gets assign...