Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

08/01/2024

12:52 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hi,
Actually that timing issues were resolved and ping performance also well as of now without packet loss. And no... Bhardwaj Kotha

07/31/2024

03:39 PM Software Development: RE: Receive and send data using vlan tag

Bhardwaj
There should be no devicetree changes necessary to use the VLAN feature of the Ethernet.
You verified that... Tim Iskander

05:55 AM Software Development: Receive and send data using vlan tag

Hi,
I am working on ethernet using vlan. I had used the ip command to create the vlan after that some data sent f... Bhardwaj Kotha

07/25/2024

07:47 PM Software Development: RE: how to access gpio using pio ip core in c code

Hello,
I would look at the avalon memory mapped slave address in your signal tap. It's possible the hps is reques... Gregory Gluszek

07/24/2024

07:11 AM Software Development: RE: how to access gpio using pio ip core in c code

Hi,
Yes, I am verified in Signal Tap only. and as off now like, we are able to do read and write HPS to FPGA using... Bhardwaj Kotha

07/23/2024

04:12 PM Software Development: RE: how to access gpio using pio ip core in c code

It looks like you posted a couple different versions of your C code. Which one are you running and what does the outp... Gregory Gluszek

07/22/2024

03:16 PM Software Development: RE: how to access gpio using pio ip core in c code

Hi,
In my implementation, the Avalon Memory Mapped interface automatically assigned a base address in platform des... Bhardwaj Kotha