Mity CPU Platforms

05/27/2020

07:12 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: GPIO toggling/chattering while performing NAND read.

Have you had any chance to create the problem on your side, I mean since the discussion started?
ZE
From: Elbi, Z... Zafer Elbi

03:33 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA programming problems

I will do that.
Thank you very much Dan.
Dario Dario Russo

02:33 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA programming problems

Hi Dario,
You could also try using the "sync" linux command after you copy the rbf over. That should flush anythin... Daniel Vincelette

02:15 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA programming problems

Hi Dan,
Don't worry, I really appreciate your help.
Yes, running “reboot” works and it is the only way to change t... Dario Russo

12:53 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA programming problems

Hi Dario,
My apologizes for the later reply, it was a long holiday weekend in the states.
So by running "reboot... Daniel Vincelette

05/26/2020

08:05 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: GPIO toggling/chattering while performing NAND read.

Yes, exactly. We did that test before.
It doesn’t show up in 2013, but shows in 2018.
Thanks
From: redmine@criti... Zafer Elbi

07:36 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: GPIO toggling/chattering while performing NAND read.

Zafer Elbi wrote:
> Hello,
> The last post was about 2 months ago. I am having exactly the same problem.
> Our env... Jonathan Cormier

06:47 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: GPIO toggling/chattering while performing NAND read.

Hello,
The last post was about 2 months ago. I am having exactly the same problem.
Our environment uses previous mi... Zafer Elbi

05/25/2020

08:39 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA programming problems

Hi Dan,
thank you very much for helping me with this problem.
Attacched you can find the boot logs for the three ca... Dario Russo

05/22/2020

05:08 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA programming problems

Hi Dario,
Thank you for the bootlog and answering my questions.
If you are seeing the yellow led toggle in u-bo... Daniel Vincelette

07:59 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA programming problems

Hi Dan,
yes, I still have the multiple boots problem.
1) I'm not changing the SDRAM bridge configuration between bu... Dario Russo

05/21/2020

01:01 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA programming problems

Hi Dario,
If you are still seeing it take multiple boots to load the "new" rbf from u-boot then it shouldn't be a ... Daniel Vincelette

08:18 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA programming problems

I checked the preloader and uboot and are updated. I noticed that in the bootlog the bridges are not initialized:
... Dario Russo

05/17/2020

07:07 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA programming problems

Hi Mike,
thank you for the detailed answer. I don’t used interruputs and UART or SPI, but I use the sdram bridge. Th... Dario Russo

11:44 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: FPGA programming problems

Hi Dario,
In your FPGA project, did you modify any of the HPS peripheral settings over your standard load? For ex... Michael Williamson

07:17 AM MitySOM-5CSX Altera Cyclone V FPGA Development: FPGA programming problems

Hi,
I’m working with MitySOM-5CSX-H6-42A development kit and I would like to solve some annoying problems. After gen... Dario Russo