Activity
From 02/23/2022 to 03/24/2022
03/21/2022
- DV 12:02 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: MitySOM 5CSX-H6-53B-RC not booting
- Hi Franz,
I don't believe changing the pin mux like you have would cause the preloader to hang at initializing the DDR, this normally occurs if the row width wasn't adjusted to account for the extra size. Also you are right the row ad...
03/16/2022
- DV 08:21 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Differences in 5CSE-L2-3Y8-RC production runs?
- Hi Lucas,
That is an interesting finding, I'm not aware of any reports of lot to lot clock instabilities. Are you passing the HPS user clock to the FPGA as your main clock source for your FPGA design or is your FPGA being clocked by a... - Hello. We've been doing some troubleshooting on prototype units that use the 5CSE-L2-3Y8-RC for DSP on the FPGA end and further treatment on the ARM CPU side and were puzzled by two units with fairly similar behavior on the analog front ...
- FS 05:39 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: MitySOM 5CSX-H6-53B-RC not booting
- Hello Dan,
Unfortunately, the boot still stalls with SDRAM_SCRUBBING enabled. As for the HPS instance, the only differences are the added FPGA to HPS interface and a few different peripheral pins which are an added SPIM0 pin and no QS...
03/09/2022
- DV 12:12 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: MitySOM 5CSX-H6-53B-RC not booting
- Hi Franz,
This hang might be due to not enabling SDRAM_SCRUBBING in the bsp-editor, as described in our bootloader build instructions step 9 (https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_uboot_181)
I ... - FS 03:30 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: MitySOM 5CSX-H6-53B-RC not booting
- Hello Dan,
I have changed the hps row address width from 15 to 16 for the MitySOM 5CSX-H6-53B-RC and added package skew compensation, IO standard and output termination lines for the extra hps address in the qsf file which gets assign...