Mity CPU Platforms » MitySOM-A5

08/14/2026

MF 07:12 PM PCB Development: RE: MitySOM Standard Carrier Board FMC pin assignment typo

Hi Max,
I reviewed your pinout and it looks correct to me.
One thing to mention is that I have posted our FMC example design and Wiki page here: [[A5E-FMC-Example]]. You obviously don't need to use this example design as you presum... Mike Fiorenza

MK 05:33 PM PCB Development: RE: MitySOM Standard Carrier Board FMC pin assignment typo

Hello Mike, thank you so much for your help!!!
I'va attached my pin assignment table with fixes. Can you please take a look and see if exerything is correct. Meanwhile, I'll try to compile with these modifications.
Thanks,
Max Maxim Kanevsky

MF 05:20 PM PCB Development: RE: MitySOM Standard Carrier Board FMC pin assignment typo

Hi Max,
You are correct, it is a typo in the FPGA Pin column and not a board issue. Both nets route correctly on the carrier and on the SoM.
Your D12 row is the good one:
* D12 (LA05_N), HVIO route: SoM pin J1-C12, HVIO_6A_12, F... Mike Fiorenza

MK 04:29 PM PCB Development: RE: MitySOM Standard Carrier Board FMC pin assignment typo

In addition to previous message, pin H8 also doesn't seems to be right connection (VR31) Maxim Kanevsky

MK 03:44 PM PCB Development: MitySOM Standard Carrier Board FMC pin assignment typo

Hello dear Sir/Madam,
I found some small typo in document: MitySOM-A5E-Standard-Development-Kit-Datasheet.pdf (inside document: 60-000098 Rev 1A):
- in table Table 17: J3 Connector Pin Assignments, pin C10 assigned to FPGA Pin: BR22
... Maxim Kanevsky

08/13/2026

MF 02:43 PM FPGA Development: RE: PCIE_RP example design - IPs question

Eleonora,
Thanks for the details. The short answer is that make jic is most likely building from the cores you edited. The Makefile make jic flow is essentially the same as hitting the compile button in Quartus, just with an extra ass... Mike Fiorenza

EH 01:41 PM FPGA Development: PCIE_RP example design - IPs question

Good morning,
I'm still trying to run the PCIe_RP example design. As we have discovered, the device that is on the board is not the one that the project was generated for, so when I changed the device Quartus needed me to update the cor... Eleonora Haralanova

08/06/2026

MK 06:31 PM FPGA Development: RE: HPS to FPGA Manager (Memory-Mapped) question

Hello Mike,
Thanks a lot for your reply.
We used this offset 0x4000_0000 (1 GB) and we got the expected reply from/to our registers!!!
Thanks for your refferal to memtool. We tested memtool, but need our application as well.
Than... Maxim Kanevsky

MF 06:08 PM FPGA Development: RE: HPS to FPGA Manager (Memory-Mapped) question

Hi Maxim,
Thanks for sending the project along, that made this much easier to answer.
*On fpgaregister.h.* Yes, it works for the full HPS to FPGA bridge. There is nothing in that header that is specific to the Lightweight bridge, i... Mike Fiorenza

MK 04:56 PM FPGA Development: HPS to FPGA Manager (Memory-Mapped) question

Hello dear Sir/Madam!!!!
we have again some question.
Based on your A5ED-B64-144-SRC-X/mitysom-a5e-ref-dma Example Desigmn, we added custom DMA Loopback (this is already working for us) and additional HPS to FPGA Manager 64 bit Data,... Maxim Kanevsky

07/30/2026

MF 02:46 PM FPGA Development: RE: Custom Loopback based on mSG-DMA Example Design

Max,
Glad to hear you have it working!
After giving this another thought, my guess may be that your FPGA design may still have been based off my previous FPGA design example. Then when I posted the new release, you may have just ta... Mike Fiorenza

MK 02:32 PM FPGA Development: RE: Custom Loopback based on mSG-DMA Example Design

Hello Mike,
Thanks a lot for your help.
I've implemented all the points you've mentioned.
This is very strange, I don't understand how this happened that SMMU was disabled and A5E Cache Coherency and DMA's had different setting than... Maxim Kanevsky

07/29/2026

DK 09:30 AM FPGA Development: RE: Custom Loopback based on mSG-DMA Example Design

> First things first: our example design is not a loopback.
> ...
It was understood after analyzing the example C code. But the first Visio picture is taken directly from documentation. Please update it.
Dmitry Kirilin

07/28/2026

MF 09:57 PM FPGA Development: RE: Custom Loopback based on mSG-DMA Example Design

Hi Maxim,
Thanks for the detailed write-up, and thanks especially for attaching the archive. I pulled your project apart and diffed it against our reference design, and I think I found your problem. Let me answer your example design q... Mike Fiorenza

MK 07:33 PM FPGA Development: Custom Loopback based on mSG-DMA Example Design

Dear Sir/Madam,
We are using your mSG-DMA Example Design and trying to make our custom Loopback based on this example design.
Please see attached to this message PDF file with drawings of Example Design and our Custom Loopback based ... Maxim Kanevsky