MitySOM-A5E PCIe Gen 4x4 RP Example Project¶

Overview¶

This example demonstrates using the Agilex 5 PCIe Hard IP in a root port (RP) configuration at Gen 4 (16 GT/s) link rates with x4 data lanes. In this example, the m.2 M-Key (typically supporting NVME SSD drives) of the MitySOM-A5E Standard Development Kit is used for testing the interface.

This project is basically the same as the MitySOM-A5E PCIe Gen 3x4 RP Example Project but the PCIe Hard IP has been configured to support Gen 4 (16 GT/s) rates instead of Gen 3. It will down shift to Gen 3 or lower Rates during the link negotiation phase. Please follow the instructions on the mentioned project link for details about building the FPGA, project, and running tests.

Supported Hardware¶

PCIe Gen-4 requires using Speed Grade "-4S" or higher FPGA / SOM devices.

• MitySOM-A5E Standard Development Kit Baseboard
  • A5ED-B64-188-SRC-X (default)
  • A5ED-B64-144-SRC-X