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Non-FPGA module NAND Timings
Added by Thomas Catalino over 12 years ago
(Posted on behalf of a customer)
In the wiki it says that without a FPGA the NAND access changes: "... on the Industrial I/O host board, by adding additional wait states to the default NAND timings (contact critical link for details). "
I guess this must be a driver change in Linux and uBoot. Can you supply this information?
Replies (1)
RE: Non-FPGA module NAND Timings - Added by Michael Williamson over 12 years ago
Hi,
Yes, currently the NAND timings are set up in the u-Boot code in line 290 of the file:
u-boot/board/davinci/mityomapl138/mityomapl138.c
The current linux kernel port for the MityDSP-L138 family of SOMs does not modify the NAND timings, so you will need to modify u-Boot to alter the NAND parameters. Instructions for building u-Boot and installing it can be found "here"::http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Das_U-Boot_Port.
NOTE: you only need to do modify the NAND timings if you want to run an FPGA-less version of the SOM on the Industrial I/O devkit host board and use the on-board NAND. If you are designing a custom board or are not using the NAND, it's unlikely you will need to modify the default timings (they should work with the part if you don't have a pile of stubs hanging off the EMIFA lines of your custom board design).
We discovered this issue during temperature testing using an Industrial I/O devkit as the test platform for FPGA-less SOM modules. During the test, I added 1 clock to each of the setup, strobe, and hold times for both read and write. The errors cleared. We have not gone back to try to optimize the timings or wring out which exact lines were ringing and what phase of the EMIFA transaction, as this configuration really isn't a proper design combination for final products.
Let me know if you need further details.
-Mike
