Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

Please make sure that any unused IO pins on your FPGA design are "floating" and not "pulled-down" in the bitstream generation options of the Xilinx tools.

By default, unused I/Os are pulled-down. That can cause pins on the EMIFA bus (and others to the OMAP-L138, like the NMI, etc.) to be driven low which can create a lot of problems.

If this is not the issue, please let me know.

To deactivate the ethernet interface, in u-Boot set the ethernet config to "0" using the "config set" command if you are not using ethernet.

-Mike

Mike,

The unused I/O pins in our FPGA design seems to be the culprit.

Here a comment from our hardware engineer.

It's actually not good to leave pins floating that are totally unused.
I'll try to put "floats" on all the EMIF pins and pulldowns on all the
unused ones, when I get a chance.

What do you think about that?

Thanks again for your help!

-François

The approach by your HW designer is fine.

Tri-stating the unused lines that are connected to the EMIFA and IRQ lines is really they key, but you need to explicitly do that in your code if you want to leave other pins as pulled down.

The tri-stating unused lines should not be a problem, as that is how the FPGA comes up when it is not configured. There may be a slightly larger power consumption (but very small).

Your hardware designer is free to specifically pull down unused pins, but you can't pull down pins that are connected (see the UCF) just because the FPGA is not actively driving them. This is the default behavior when the MAP process strips out pins that aren't driven in VHDL and you don't update the bitstream generation options.

-Mike

Thanks Mike for answer.

I forwarded your last comment to our HW engineer.

Chances are I will not get other questions from him. He is extremely busy theses days. I will create a new discussion thread if he comes back with other question/comments.

Consider this ticket closed.

Regards,

-François