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FPGA Memory Size
Added by LSA Autonomy over 11 years ago
The standard FPGA memory available to the arm processor within angstrom is currently limited to 2k.
From what we can gather there are many places that could work together to create this limit:
Flash code
uBoot
FPGA vhdl
Linux driver.
We understand that cs4 is the chip select associated with the arm, and we see in the vhdl where the address decoding limits the memory space.
Which piece of software configures the memory controller for cs4, and which places do we need to recompile, and update to open this memory area to where the limits are the number of address lines connected to the FPGA.
Thanks!
Replies (2)
RE: FPGA Memory Size - Added by Michael Williamson over 11 years ago
As mentioned on the EMIFA wiki page, all of our FPGA fabric and drivers use CE5 space (0x66000000), for the ARM or the DSP (where did you find information on CS4? I thought we had scrubbed the documentation...).
Right now, the uBoot code configures all of the wait states and settings for the EMIFA in board/davinci/mityomapl138/mityomapl138.c. The kernel port for the MityDSP-L138 does not modify the EMIFA configure, but it could be modified (usually in the baseboard file) if you would prefer to stay out of the u-Boot code. I don't have any example code, but you should be able to lift the code from the u-Boot section and clone in in the kernel if you choose.
You will need to modify the uBoot code or the kernel to configure the chip select space you desire to use. The u-boot may be easier, it's really your decision.
You are free to use any of the CE0, CE2, CE4, or CE5 address spaces (CE5 can be used if you omit any of our framework). There are only 14 address lines on the OMAP-L138 EMIFA and that are all connected to the FPGA, so for a 16 bit bus you can logically address 32K bytes per chip select. Normally, we find that we rarely need that much addressable space.... we use FIFO's or provide auto-incrementing pointer registers to decode larger memory regions.
For access to a different CS space, you'll need to write a custom driver that maps the memory in to your register / memory design. Not sure exactly what you are trying to do, but it should be fairly straightforward to Map IO Memory operation and make use of it. That is was fpga_ctrl.c does.
Hope this helps....
-Mike
RE: FPGA Memory Size - Added by LSA Autonomy over 11 years ago
You are correct we are looking at cs5 as well.
32k would probably be sufficient. We typically prefer to provide the information in a flat manner to offload the CPU from parsing, or having to copy out all the information instead of the one or two words you need to use.
How much space is the current cs5 and the driver configured to use in uBoot? Is it all 32k?
and found the wait state information, but little on the size of the area.
~JM
