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EMIFA Clock not present
Added by Mary Frantz over 11 years ago
The EMIFA clock is not active on our custom board. This signal goes high and stays there. This is true after booting Linux or just U-boot.
Here's the U-boot log:
OMAP-L138/AM-1808/AM-1810 initialization passed!
Booting TI User Boot Loader
UBL Version: 1.65:2.27.1 BuiltFeb 8 2011 12:15:05
UBL Flashtype: SPI
Starting SPI Memory Copy...
Valid magicnum, 0x55424CBB, found at offset 0x00010000.
DONE
Jumping to entry point at 0xC1080000.
U-Boot 2009.11 (Mar 31 2011 - 19:39:18)
I2C: ready
DRAM: 128 MB
NAND: 256 MiB
MMC: davinci: 0
In: serial
Out: serial
Err: serial
ARM Clock : 300000000 Hz
DDR Clock : 150000000 Hz
EMIFA CLock : 100000000 Hz
DSP Clock : 300000000 Hz
ASYNC3 Clock : 150000000 Hz
Enet config : 2
MMC 0 Enable : 0
Resetting ethernet phy
Net: Ethernet PHY: GENERIC @ 0x03 [0x8]
Hit any key to stop autoboot: 0
U-Boot >
Is this output disabled by default? We are using pin 171 from the MityDSP-OMAPL138 SOM.
Also, we plan to change the cpu frequency to 456 MHz at boot using a script command.
echo 456000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed
Will this command change the EMIFA clock frequency?
Mary
Replies (4)
RE: EMIFA Clock not present - Added by Michael Williamson over 11 years ago
Hmm.... The EMA_CLK output should be active on power up, is it possible on your customer board there is contention. There is a 50 Ohm series resistor in line on the module side. You are using a non-FPGA based module, right?
Changing the frequency will impact the EMIFA clock frequency due to the clock tree design. I think you will get 91.2 MHz (456/5) when you boost the CPU frequency up to 456 MHz.
-Mike
RE: EMIFA Clock not present - Added by Mary Frantz over 11 years ago
Yes, we are using non-FPGA modules. Double checked the schematic, reprobed, tried different SOM modules, checked the clock on your Industrial IO board. Still no clock.
We are doing asynchronous read/writes to our own FPGA and just need some sort of clock to run the internal logic. We'll probably use a different clock source.
Mary
RE: EMIFA Clock not present - Added by Mary Frantz about 11 years ago
We are baffled. I have checked the following registers using a JTAG emulator (Blackhawk USB560 on the DSP side).
The hardware is MityDSP-OMAPL138 SOM without FPGA attached to an Industrial I/O board. This kernel is your MDK_2012-08-10 with SATA support added. Also, a script has been run to set the CPU clock to 456 MHz.
echo 456000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed
PINMUX6 = 0x00110001 bits 0 - 3 = 1 set output to EMA_CLK
CFGCHIP3 = 0x0000FE10 DIV4P5ENA = 0 disable 4.5 divide
EMA_CLKSRC = 0 PLLCTRL_SYSCLK3
PLL0:
PLLM = 0x00000012 multiply by 19 (24 MHz x 19 = 456 MHz)
PREDIV = 0x00008000 divide by 1
PLLDIV3 = 0x00008004 divide by 5 (456 MHz / 5 = 91.2 MHz)
I ran a diagnotsic gel script from TI to check the PSC status:
C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: | PSC0 Information | C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: C674X_0: GEL Output: State Decoder: C674X_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off) C674X_0: GEL Output: 1 = SyncReset (reset assered, clock on) C674X_0: GEL Output: 2 = Disable (reset de-asserted, clock off) C674X_0: GEL Output: 3 = Enable (reset de-asserted, clock on) C674X_0: GEL Output: >3 = Transition in progress C674X_0: GEL Output: C674X_0: GEL Output: Module 0: EDMA3CC (0) STATE = 3 C674X_0: GEL Output: Module 1: EDMA3 TC0 STATE = 3 C674X_0: GEL Output: Module 2: EDMA3 TC1 STATE = 3 C674X_0: GEL Output: Module 3: EMIFA (BR7) STATE = 3 C674X_0: GEL Output: Module 4: SPI 0 STATE = 2 C674X_0: GEL Output: Module 5: MMC/SD 0 STATE = 3 C674X_0: GEL Output: Module 6: AINTC STATE = 3 C674X_0: GEL Output: Module 7: ARM RAM/ROM STATE = 3 C674X_0: GEL Output: Module 9: UART 0 STATE = 3 C674X_0: GEL Output: Module 10: SCR 0 (BR0/1/2/8) STATE = 3 C674X_0: GEL Output: Module 11: SCR 1 (BR4) STATE = 3 C674X_0: GEL Output: Module 12: SCR 2 (BR3/5/6) STATE = 3 C674X_0: GEL Output: Module 13: PRUSS STATE = 0 C674X_0: GEL Output: Module 14: ARM STATE = 3 C674X_0: GEL Output: Module 15: DSP STATE = 3 C674X_0: GEL Output: C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: | PSC1 Information | C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: C674X_0: GEL Output: State Decoder: C674X_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off) C674X_0: GEL Output: 1 = SyncReset (reset assered, clock on) C674X_0: GEL Output: 2 = Disable (reset de-asserted, clock off) C674X_0: GEL Output: 3 = Enable (reset de-asserted, clock on) C674X_0: GEL Output: >3 = Transition in progress C674X_0: GEL Output: C674X_0: GEL Output: Module 0: EDMA3CC (1) STATE = 3 C674X_0: GEL Output: Module 1: USB0 (2.0) STATE = 3 C674X_0: GEL Output: Module 2: USB1 (1.1) STATE = 3 C674X_0: GEL Output: Module 3: GPIO STATE = 3 C674X_0: GEL Output: Module 4: UHPI STATE = 3 C674X_0: GEL Output: Module 5: EMAC STATE = 3 C674X_0: GEL Output: Module 6: DDR2 and SCR F3 STATE = 3 C674X_0: GEL Output: Module 7: MCASP0 + FIFO STATE = 3 C674X_0: GEL Output: Module 8: SATA STATE = 3 C674X_0: GEL Output: Module 9: VPIF STATE = 3 C674X_0: GEL Output: Module 10: SPI 1 STATE = 3 C674X_0: GEL Output: Module 11: I2C 1 STATE = 2 C674X_0: GEL Output: Module 12: UART 1 STATE = 3 C674X_0: GEL Output: Module 13: UART 2 STATE = 3 C674X_0: GEL Output: Module 14: MCBSP0 + FIFO STATE = 3 C674X_0: GEL Output: Module 15: MCBSP1 + FIFO STATE = 3 C674X_0: GEL Output: Module 16: LCDC STATE = 2 C674X_0: GEL Output: Module 17: eHRPWM (all) STATE = 3 C674X_0: GEL Output: Module 18: MMC/SD 1 STATE = 2 C674X_0: GEL Output: Module 19: UPP STATE = 3 C674X_0: GEL Output: Module 20: eCAP (all) STATE = 3 C674X_0: GEL Output: Module 21: EDMA3 TC2 STATE = 3 C674X_0: GEL Output: Module 24: SCR-F0 Br-F0 STATE = 3 C674X_0: GEL Output: Module 25: SCR-F1 Br-F1 STATE = 3 C674X_0: GEL Output: Module 26: SCR-F2 Br-F2 STATE = 3 C674X_0: GEL Output: Module 27: SCR-F6 Br-F3 STATE = 3 C674X_0: GEL Output: Module 28: SCR-F7 Br-F4 STATE = 3 C674X_0: GEL Output: Module 29: SCR-F8 Br-F5 STATE = 3 C674X_0: GEL Output: Module 30: Br-F7 (DDR Contr) STATE = 3 C674X_0: GEL Output: Module 31: L3 RAM, SCR-F4, Br-F6 STATE = 3
So, EMIFA is enabled in the PSC controller. The pin is enabled in the PINMUX register. The output goes high briefly after reset then tristates. I don't understand why.
We really need this output.
Mary
RE: EMIFA Clock not present - Added by Mary Frantz about 11 years ago
The clock started working after some FPGA machinations.
New problem:
We can read registers from the FPGA but can't write:
Here's the code on the ARM side:
#define LEN_FPGA_MEM 256
void OMAP_readFPGA(unsigned int *pData, unsigned int off, int n)
{
int fd;
uint16_t *vaddr;
// Access FPGA memory mapped registers
fd = open("/dev/mem", O_RDWR | O_SYNC); // READ/WRITE, NON-CHACHED
// TODO: set size of FPGA memory (use instead of n)
vaddr = (uint16_t *)mmap(NULL, LEN_FPGA_MEM, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0x60000000 ); // get virtual address for L3_CBA_RAM 0x80000000
//vaddr = (unsigned int *)mmap(NULL, sizeof(int), PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0x80000000 + (off * sizeof(int))); // get virtual address for L3_CBA_RAM 0x80000000
//memcpy(pData, (char *)(vaddr + off), n);
*pData = vaddr[off >> 1];
// memcpy(pData, (vaddr + off), n);
munmap(vaddr, LEN_FPGA_MEM);
close(fd);
}
void OMAP_writeFPGA(unsigned int *pData, unsigned int off)
{
int fd;
//unsigned int *vaddr;
uint16_t *vaddr;
// Access FPGA memory mapped registers
fd = open("/dev/mem", O_RDWR | O_SYNC); // READ/WRITE, NON-CHACHED
vaddr = (uint16_t *)mmap(NULL, LEN_FPGA_MEM, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0x60000000 ); // get virtual address for FPGA registers 0x60000000
//vaddr = (unsigned int *)mmap(NULL, sizeof(int), PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0x80000000 + (off * sizeof(int))); // get virtual address for L3_CBA_RAM 0x80000000
//memcpy(pData, (char *)(vaddr + off), n);
vaddr[off >> 1] = *pData;
msync(vaddr, LEN_FPGA_MEM, MS_SYNC);
// memcpy(vaddr + off, &data, 2);
munmap(vaddr, LEN_FPGA_MEM);
close(fd);
}
The register is loaded with and initial value (0xDEAD) then a new value is written (0x00A5). The register is read again but the original initial value is still there (0xDEAD).
Note: the "off" parameter is the byte address offset from the starting address, so is always a multiple of two.
Am I using mmap correctly? Do any of the EMIF registers need to be changed? We are using CS2.
Mary
