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Programming the FPGA - Loading via CPU

Added by Jesus Alejandro Alvarez Trejo over 3 years ago

Hi, Good Day, I am trying to load the FPGA via CPU, but I would like to know: How can I configure the slave select mode in the FPGA?. I read the Xilinx Spartan-6 configuration guide, but it is not enough clear.

"The FPGA has been connected to the on board CPU such that the CPU asynchronous interface may be used to program it using the slave select mode of configuration (8-bit parallel mode using chip select 5). In slave select mode, the CPU loads the binary configuration data for the FPGA from non-volatile storage and transmits it to the FPGA. For details regarding slave select programming, please refer to the Xilinx Spartan-6 configuration guide. Critical Link provides two software mechanisms for loading the FPGA with this technique, via u-Boot or via Linux FPGA drivers (custom by critical link). Both require a .bin file (not an .mcs file) from the Xilinx Impact tool."

Thanks,
Regards.


Replies (4)

RE: Programming the FPGA - Loading via CPU - Added by Jonathan Cormier over 3 years ago

I don't understand the difference between this question and your last question. https://support.criticallink.com/redmine/boards/10/topics/5138

The programming guide from which you grabbed the above paragraph, includes the two ways that we program the FPGA via the CPU using the slave select mode. https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Programming_the_FPGA#Loading-via-CPU

You shouldn't have to manually configure the slave select mode.

RE: Programming the FPGA - Loading via CPU - "ERROR LOADING" - Added by Jesus Alejandro Alvarez Trejo over 3 years ago

Hello, Good Day

I am trying to load the FPGA using https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Programming_the_FPGA vía CPU, I already created the .bin file to do the first test. I am using the PROFIBUS Development Kit with the MitySOM-1810F module.

First:

1.- I connected the DB-9 connector to used the serial communication (RS-232) and I am using a serial monitor software (Teraterm) to look the data that is being transferred through serial connection.
2.- I change the network configuration and I assigned and Static IP address for the card.
3.- I established an Ethernet communication between the card and the computer, and I tested the communication pinging through Ethernet Connection. It's show below.

root@mityomapl138:~# ping 192.168.50.3
PING 192.168.50.3 (192.168.50.3): 56 data bytes
64 bytes from 192.168.50.3: seq=0 ttl=128 time=1.284 ms
64 bytes from 192.168.50.3: seq=1 ttl=128 time=1.275 ms
--- 192.168.50.3 ping statistics ---
2 packets transmitted, 2 packets received, 0% packet loss
round-trip min/avg/max = 1.275/1.279/1.284 ms

4.- I used the "printenv" command to see the environment settings. It's shown below:

U-Boot > printenv
bootdelay=3
baudrate=115200
bootfile="uImage"
flashuboot=tftp 0xc0700000 mityomap/u-boot-ubl.bin; sf probe 0; sf erase 0x10000 0x80000; sf write 0xc0700000 0x10000 ${filesize}
flashkernel=tftp 0xc0700000 mityomap/uImage; sf probe 0; sf erase 0x100000 0x280000; sf write 0xc0700000 0x100000 ${filesize}
flashubl=tftp 0xc0700000 mityomap/UBL_SPI_MEM.ais; sf probe 0; sf erase 0 0x10000; sf write 0xc0700000 0 0x10000
flashrootfs=tftp 0xc2000000 mityomap/mityomap-base-mityomapl138.jffs2; nand erase 0 0x08000000; nand write.jffs2 0xc2000000 0 ${filesize}
mtdids=nand0=nand
mtdparts=mtdparts=nand:128M(rootfs),-(userfs)
bootargsbase=mem=96M console=ttyS1,115200n8
flashargs=setenv bootargs ${bootargsbase} ${mtdparts} root=/dev/mtdblock0 rw,noatime rootfstype=jffs2
bootargs=mem=96M console=ttyS1,115200n8 mtdparts=nand:128M(rootfs),-(userfs) root=/dev/mtdblock0 rw,noatime rootfstype=jffs2
autoload=no
bootcmd=sf probe 0; sf read 0xc0700000 0x100000 0x280000; bootm 0xc0700000
ipaddr=192.168.50.1
gatewayip=192.168.0.254
netmask=255.255.255.0
serverip=192.168.50.3
stdin=serial
stdout=serial
stderr=serial
ethaddr=00:50:c2:bf:8d:b2
ver=U-Boot 2009.11 (Mar 31 2011 - 19:39:18)
Environment size: 1174/65532 bytes

5.-I used the "uBoot> tftp 0xC0700000 yourserver:/path/to/fpga.bin" to Download the .bin file to memory. It's shown below.

U-Boot > tftp 0xC0700000 192.168.50.3:D:/first.bin
Using device
TFTP from server 192.168.50.3; our IP address is 192.168.50.1
Filename 'D:/first.bin'.
Load address: 0xc0700000
Loading: T T T T
And the error is that only shows the word "T" when is loading the FPGA and It does not load the FPGA.

Thanks for your time, regards

Alex

RE: Programming the FPGA - Loading via CPU - "ERROR LOADING" - Added by Jonathan Cormier over 3 years ago

Jesus Alejandro Alvarez Trejo wrote:

Hello, Good Day

I am trying to load the FPGA using https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Programming_the_FPGA vía CPU, I already created the .bin file to do the first test. I am using the PROFIBUS Development Kit with the MitySOM-1810F module.

First:

1.- I connected the DB-9 connector to used the serial communication (RS-232) and I am using a serial monitor software (Teraterm) to look the data that is being transferred through serial connection.
2.- I change the network configuration and I assigned and Static IP address for the card.
3.- I established an Ethernet communication between the card and the computer, and I tested the communication pinging through Ethernet Connection. It's show below.

root@mityomapl138:~# ping 192.168.50.3
PING 192.168.50.3 (192.168.50.3): 56 data bytes
64 bytes from 192.168.50.3: seq=0 ttl=128 time=1.284 ms
64 bytes from 192.168.50.3: seq=1 ttl=128 time=1.275 ms

--- 192.168.50.3 ping statistics ---
2 packets transmitted, 2 packets received, 0% packet loss
round-trip min/avg/max = 1.275/1.279/1.284 ms

Your ping command was run while booted into linux. You should run it while in u-boot to prove you have network communication working.

4.- I used the "printenv" command to see the environment settings. It's shown below:

U-Boot > printenv
bootdelay=3
baudrate=115200
bootfile="uImage"
flashuboot=tftp 0xc0700000 mityomap/u-boot-ubl.bin; sf probe 0; sf erase 0x10000 0x80000; sf write 0xc0700000 0x10000 ${filesize}
flashkernel=tftp 0xc0700000 mityomap/uImage; sf probe 0; sf erase 0x100000 0x280000; sf write 0xc0700000 0x100000 ${filesize}
flashubl=tftp 0xc0700000 mityomap/UBL_SPI_MEM.ais; sf probe 0; sf erase 0 0x10000; sf write 0xc0700000 0 0x10000
flashrootfs=tftp 0xc2000000 mityomap/mityomap-base-mityomapl138.jffs2; nand erase 0 0x08000000; nand write.jffs2 0xc2000000 0 ${filesize}
mtdids=nand0=nand
mtdparts=mtdparts=nand:128M(rootfs),-(userfs)
bootargsbase=mem=96M console=ttyS1,115200n8
flashargs=setenv bootargs ${bootargsbase} ${mtdparts} root=/dev/mtdblock0 rw,noatime rootfstype=jffs2
bootargs=mem=96M console=ttyS1,115200n8 mtdparts=nand:128M(rootfs),-(userfs) root=/dev/mtdblock0 rw,noatime rootfstype=jffs2
autoload=no
bootcmd=sf probe 0; sf read 0xc0700000 0x100000 0x280000; bootm 0xc0700000
ipaddr=192.168.50.1
gatewayip=192.168.0.254
netmask=255.255.255.0
serverip=192.168.50.3
stdin=serial
stdout=serial
stderr=serial
ethaddr=00:50:c2:bf:8d:b2
ver=U-Boot 2009.11 (Mar 31 2011 - 19:39:18)

Environment size: 1174/65532 bytes

5.-I used the "uBoot> tftp 0xC0700000 yourserver:/path/to/fpga.bin" to Download the .bin file to memory. It's shown below.

U-Boot > tftp 0xC0700000 192.168.50.3:D:/first.bin
Using device
TFTP from server 192.168.50.3; our IP address is 192.168.50.1
Filename 'D:/first.bin'.
Load address: 0xc0700000
Loading: T T T T

And the error is that only shows the word "T" when is loading the FPGA and It does not load the FPGA.

What tftp server are you using? In my experience most tftp servers are configured to look into a specific directory and so you can't provide the drive letter in the path D:/first.bin. If the tftp server is pointed to D:/ then the tftp path would be first.bin

The T's could indicate it can't find the server or the network isn't setup correctly. Running the ping command in u-boot would let us know that networking is working in u-boot.

RE: Programming the FPGA - Loading via CPU - Added by Jesus Alejandro Alvarez Trejo over 3 years ago

Hello, good day

I load the FPGA with "Example loading the .bin file over the serial port using Kermit" because it was easier but I will continue trying with TFTP server.

U-Boot > loadb 0xC0700000
  1. Ready for binary (kermit) download to 0xC0700000 at 115200 bps...
  2. Total Size = 0x00071544 = 464196 Bytes
  3. Start Addr = 0xC0700000

Now I have other doubt because when I load the .bin file and then I check if the FPGA is loaded visually by examining the LED (D1 - TBC) which is tied to the FPGA Done signal asserted by the FPGA when it has successfully been configured, but the led is OFF therefore I loaded an example of the Critical Link Custom Product Development Disk which includes an examples about The FPGA and it works because the led is On, I do not know if I should use an special configuration to create the .bin file.

1.- I did a simple project to load the FPGA. it's shown below

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity do is
Port ( A : out STD_LOGIC;
B : out STD_LOGIC;
C : out STD_LOGIC;
D : out STD_LOGIC);
end do;

architecture Behavioral of do is

begin

A <= '1';
B <= '0';
C <= '1';
D <= '0';

end Behavioral;

2.- The implementation Constraints File:

NET "A" LOC = "K13" | IOSTANDARD = LVCMOS33; #OUT A 
NET "B" LOC = "K12" | IOSTANDARD = LVCMOS33; #OUT B
NET "C" LOC = "L13" | IOSTANDARD = LVCMOS33; #OUT C
NET "D" LOC = "L12" | IOSTANDARD = LVCMOS33; #OUT D

3.- The design properties image is attached.

Thanks for your time.
Alex

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