Forums » Software Development »
uPP digital loopback
Added by Scott Whitney over 12 years ago
Hello,
I have a linux driver module to test the uPP in digital loopback. I saw some odd behavior in regards to the clock divisors on Channels A and B. I have the module set to loopback 64 bytes from channel A to channel B. If I set the divisor on channel A to 1, but leave the divisor on channel B to 0 the transferred data in the receive buffer is duplicated as if the Channel B clock is running 2x from the Channel A clock. I thought the xmitter should be driving the clock, even in DLB. Joe from TI thought this was odd behavior.
My concern is possible contamination of clock lines. Could this just be leakage, I don't have anything loaded on the FPGA, of the clock line? Can I assume when I use both Channels A and B and any set as receivers are getting the clock line driven by the FPGA that this shouldn't be a problem? Thanks in advance, Scott
Replies (2)
RE: uPP digital loopback - Added by Gregory Gluszek over 12 years ago
Hi Scott,
As far as I know we have not seen any issue like what you're describing when using a uPP clock driven by the FPGA. Given, we haven't done much work with the uPP in DLB, so it could be a problem unique to that setup.
Another thing to consider in regards to what you are seeing is the source of the UPP_2xTXCLK. According to Section 2.2 of the uPP user's guide this needs to be twice the speed of your desired I/O clock. The UPP_2xTXCLK can either be driven externally or by ASYNC3 (which should be the default, and is driven by one of system PLL settings). I know we've run into problem with this in the past and it has manifested itself in odd ways, so you may want to see how your system is setup. See Section 11.5.17 of the OMAPL138 System Reference Guide for details on UPP_2xTXCLK selection.
\Greg
RE: uPP digital loopback - Added by Scott Whitney over 12 years ago
Greg,
I'm using the default ASYNCH3 clock which is PLL_SYSCLK1 I think. This should be divided down automatically. Since I am just using this to test the uPP I won't worry about it and keep the Chan A and Chan B clock divisors equal. Thanks for your help, Scott
