Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

Hello,ALL
I want to test the DspFpgaSpi, but not successfully setup,Could anyone give me some instructions?
Before I have successfully tested the GPIO from your help, Thank you very much!

This the VHDL code Setup
/////////////////////////
constant CORE_SPI_MODULE : integer :=14; /*the number is found in cores_id.h*/
constant CORE_SPI_IRQ_LEVEL: integer :=1; /* communicate with DSP set 1 */
constant CORE_SPI_IRQ_VECTOR: integer :=0; ? How about this one,d,is it related to DSP ?,

------------------------------------
---SPi&FIFO components port mapping--posted by  Michael Williamson
----------------------------------
spi_core : spi
   Port Map (  
      emif_clk       => ema_clk, 
      i_ABus         => addr_r,
      i_DBus         => edi_r,
      o_DBus         => edo_arm(CORE_SPI_MODULE),
      i_wr_en        => wr_r,
      i_rd_en        => rd_r,
      i_cs           => arm_cs5_r(CORE_SPI_MODULE),
      o_irq          => irq_map(CORE_SPI_IRQ_LEVEL)(CORE_SPI_IRQ_VECTOR),
      i_ilevel       => CONV_STD_LOGIC_VECTOR(CORE_SPI_IRQ_LEVEL,2),
      i_ivector      => CONV_STD_LOGIC_VECTOR(CORE_SPI_IRQ_VECTOR,4),

-- SPI interface signals        
      o_sclk         => spi_clk,          ---These pins I have setted in ucf to map the Fpgat pins.
      o_cs_n         => spi_cs,
      o_mosi         => spi_mosi,
      i_miso         => spi_miso,

-- In/Out FIFO interfaces (NO FIRST WORD FALL THROUGH)  ///// Using the xilinx-ise to generate the FiFo Ip cores
      --    Synchronous on emif_clock
      i_fifo_depth          => "010",
      o_mosi_fifo_wr        => mosi_wr_en,
      o_mosi_fifo_rd        => mosi_rd_en,
      o_mosi_fifo_in        => mosi_din,  -- fifo data input
      i_mosi_fifo_out       => mosi_dout,
      i_mosi_write_cnt      => mosi_wr_data_count,
      i_mosi_empty             => mosi_empty,

o_miso_fifo_wr        => miso_wr_en,
      o_miso_fifo_rd        => miso_rd_en,
      o_miso_fifo_in        => miso_din,
      i_miso_fifo_out       => miso_dout,
      i_miso_read_cnt       => miso_rd_data_count,
      i_miso_empty          => miso_empty,

o_fifo_rst            => spi_fifo_rst

);

spi_ccs<=spi_cs(0);
    --------------------------

mosi_fifo : fifo_dpram64x32
        port map (
            clk => ema_clk,
            rst => spi_fifo_rst,
            din => mosi_din,
            wr_en => mosi_wr_en,
            rd_en => mosi_rd_en,
            dout => mosi_dout,
            full => open,
            empty => mosi_empty,
            data_count => mosi_wr_data_count(5 downto 0));

miso_fifo : fifo_dpram64x32
port map (
clk => ema_clk,
rst => spi_fifo_rst,
din => miso_din,
wr_en => miso_wr_en,
rd_en => miso_rd_en,
dout => miso_dout,
full => open,
empty => miso_empty,
data_count => miso_rd_data_count(5 downto 0));
--------------------------------------------------------------

The DSP code
--------------------------
Using the existing function in DspFpgaSpi.cpp
---
---
-------------------------
char outData³²;
char inData³²;
int i;
unsigned int my_base_addr = 0x66000A00;
// Setup the address, CORE_GPIO_MODUL=14(in vhdl),14*0x80=A00,set address:0x66000A00 )
spi = new tcDspFpgaSpi((void *)my_base_addr);
// setup Chip Select
spi->ConfigCS(0, 0, 0, 1000000, tcDspFpgaSpi::ee8Bit);

while(1) {

// load TX data
                   for (i=0; i<32; i++)
       {
                         outData[i] = i;

}

// Do a SPI transfer
                    spi->Transfer(outData, inData, 32, 0);
        }
//////////////////////////////////////////////////////////////////

Best Regards
lj