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DSP to FPGA SPI Setup Question

Added by lijun yang about 6 years ago

Hello,ALL
I want to test the DspFpgaSpi, but not successfully setup,Could anyone give me some instructions?
Before I have successfully tested the GPIO from your help, Thank you very much!

This the VHDL code Setup
/////////////////////////
constant CORE_SPI_MODULE : integer :=14; /*the number is found in cores_id.h*/
constant CORE_SPI_IRQ_LEVEL: integer :=1; /* communicate with DSP set 1 */
constant CORE_SPI_IRQ_VECTOR: integer :=0; ? How about this one,d,is it related to DSP ?,

------------------------------------
---SPi&FIFO components port mapping--posted by Michael Williamson
----------------------------------
spi_core : spi
Port Map (
emif_clk => ema_clk,
i_ABus => addr_r,
i_DBus => edi_r,
o_DBus => edo_arm(CORE_SPI_MODULE),
i_wr_en => wr_r,
i_rd_en => rd_r,
i_cs => arm_cs5_r(CORE_SPI_MODULE),
o_irq => irq_map(CORE_SPI_IRQ_LEVEL)(CORE_SPI_IRQ_VECTOR),
i_ilevel => CONV_STD_LOGIC_VECTOR(CORE_SPI_IRQ_LEVEL,2),
i_ivector => CONV_STD_LOGIC_VECTOR(CORE_SPI_IRQ_VECTOR,4),
-- SPI interface signals        
o_sclk => spi_clk, ---These pins I have setted in ucf to map the Fpgat pins.
o_cs_n => spi_cs,
o_mosi => spi_mosi,
i_miso => spi_miso,
-- In/Out FIFO interfaces (NO FIRST WORD FALL THROUGH)  ///// Using the xilinx-ise to generate the FiFo Ip cores
-- Synchronous on emif_clock
i_fifo_depth => "010",
o_mosi_fifo_wr => mosi_wr_en,
o_mosi_fifo_rd => mosi_rd_en,
o_mosi_fifo_in => mosi_din, -- fifo data input
i_mosi_fifo_out => mosi_dout,
i_mosi_write_cnt => mosi_wr_data_count,
i_mosi_empty => mosi_empty,
o_miso_fifo_wr        => miso_wr_en,
o_miso_fifo_rd => miso_rd_en,
o_miso_fifo_in => miso_din,
i_miso_fifo_out => miso_dout,
i_miso_read_cnt => miso_rd_data_count,
i_miso_empty => miso_empty,
o_fifo_rst            => spi_fifo_rst
);
spi_ccs<=spi_cs(0);
--------------------------
mosi_fifo : fifo_dpram64x32
port map (
clk => ema_clk,
rst => spi_fifo_rst,
din => mosi_din,
wr_en => mosi_wr_en,
rd_en => mosi_rd_en,
dout => mosi_dout,
full => open,
empty => mosi_empty,
data_count => mosi_wr_data_count(5 downto 0));

miso_fifo : fifo_dpram64x32
port map (
clk => ema_clk,
rst => spi_fifo_rst,
din => miso_din,
wr_en => miso_wr_en,
rd_en => miso_rd_en,
dout => miso_dout,
full => open,
empty => miso_empty,
data_count => miso_rd_data_count(5 downto 0));
--------------------------------------------------------------

The DSP code
--------------------------
Using the existing function in DspFpgaSpi.cpp
---
---
-------------------------
char outData32;
char inData32;
int i;
unsigned int my_base_addr = 0x66000A00;
// Setup the address, CORE_GPIO_MODUL=14(in vhdl),14*0x80=A00,set address:0x66000A00 )
spi = new tcDspFpgaSpi((void *)my_base_addr);
// setup Chip Select
spi->ConfigCS(0, 0, 0, 1000000, tcDspFpgaSpi::ee8Bit);

while(1) {

// load TX data
for (i=0; i&lt;32; i++) {
outData[i] = i;
}
// Do a SPI transfer
spi->Transfer(outData, inData, 32, 0);
}
//////////////////////////////////////////////////////////////////

Best Regards
lj


Replies (5)

RE: DSP to FPGA SPI Setup Question - Added by Alexander Block about 6 years ago

Update and followup question from the customer:

We have made the SPI work, but transmitting the word to word is slow.(about 11 uSec to send a 24bit word).

This is the code we run in the DSP:

spi = new tcDspFpgaSpi((void *)my_base_addr);
spi->ConfigCS(0, 0, 0, 50000000, tcDspFpgaSpi::ee24Bit);
while(1)
spi->Transfer(outData, NULL, 1, 0);

We suspect that the EMIFA communication is the bottleneck.

Is this the bandwidth we should expect from EMIFA?

RE: DSP to FPGA SPI Setup Question - Added by Michael Williamson about 6 years ago

Can you check with a scope at what the clock rate is on the SPI device, and the interword write delay? I just want to confirm they are getting 50 MHz clock rate.

It might be the EMIFA transfer, but we should confirm that the SPI device is running at rate.

-Mike

RE: DSP to FPGA SPI Setup Question - Added by lijun yang about 6 years ago

Hello,Mike
Thank you for your help.
I have attached two pic
----one is the SPI bits transfer rate(This is our desired speed),

----another one is the word to word transfer rate(This is slow. We want it can be fast,Could you give us some ideas?)

If it can't work, we have to try the UPP.
Could you give us some ideas about UPP?

Than you very much.
Regards
LJ

WP_20140625_10_20_25_Pro.jpg View - SPi bits transfer rate (434 KB)

WP_20140625_10_19_52_Pro.jpg View - SPI word to word rate (461 KB)

RE: DSP to FPGA SPI Setup Question - Added by Michael Williamson about 6 years ago

What is your target update rate? Continuous?

You might try first to rip out all of the overhead on the tcDspFpgaSpi.cpp code (there is LCK_pend()/LCK_post() for serialization control, etc) and boil it down to the register writes.

You could use the UPP, but you'd need to write your own UPP to SPI interface, which should not really be required.

You might try to write a FIFO to shift register interface in the FPGA and just write that FIFO directly and not use the SPI core.

-Mike

RE: DSP to FPGA SPI Setup Question - Added by lijun yang about 6 years ago

Hello,Mike
Thank you very much.

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