Mity CPU Platforms » MitySOM-335x (ARM Cortex-A8 Based Products)

I am in the process of debugging the SMSC LAN8820 PHY on a board that has a Mityarm board used as the CPU. The PHY is connected as RGMII1, with pinmux files changed in u-boot and baseboard-mityarm335x-devkit.c. I also added this new PHY to the smsc.c driver file.I can talk to the PHY through MDIO OK, I can configure it. I also tested pinmuxing by running the RGMII-REFCLK pin to an test point and verified it is outputing 50MHz. The SMSC phy has it's own 25MHz clock connected. I force the PHY to run at 100Mb, no auto negotiation. All the registers in MDIO look OK, the PHY links correctly to a router. On the pins to the Mityarm module, RGMII1 is being used from the defaulted RGMII2 configuration from the dev board. The PHY is correctly sending a clock (25Mhz), control and rd data[3:0] to the Mityarm module (GMII1_RXD[3:0}). When I run ping on the Mityarm terminal, I can ifconfig eth1 successfully. I cannot ping out, and all the transmit RGMII phy signals are low, this include TXCLK, TXD[3:0], and TXEN.

Since the RGMII2 connection was used in the dev board, is there something more to change to make the RGMII1 bus work correctly outside of changing pin multiplexing? It looks like RGMII1 connection is disabled. but the MDIO bus is OK.