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Programming FPGA through JTAG and High speed data transfer support
Added by Bhima Shankar 3 days ago
Hello everyone,
We are currently working on a project using the MitySOM-AM57X development board, and we would appreciate some guidance on programming the FPGA via JTAG. Could anyone kindly share the detailed procedure or point us to relevant documentation or tools required for this process? Any official guidelines or community-proven steps would be very helpful to ensure we proceed correctly.
Additionally, we were exploring the example projects provided and wanted to ask — is there any driver or interface support for high-speed data transfer available out of the box?
We would be grateful for any insights, suggestions, or references.
Thank you in advance for your help!
Regards
Shankar
Replies (1)
RE: Programming FPGA through JTAG and High speed data transfer support - Added by Michael Williamson 3 days ago
Hi Shankar,
It is a US holiday today, I will add some documentation for programming via JTAG (at least a wiki page) first thing tomorrow.
In the meantime, you should be able to use any AMD / Xilinx approved POD, but you will need an adapter board that breaks out the Hirose connector on the SOM to the FPGA JTAG and the AM57x JTAG connector interfaces. I believe that one is included with the Development Kits, but I will confirm tomorrow. The breakout board should provide a standard 2mm FPGA interface that should mate directly with the standard Xilinx PODs.
After the SOM is powered, you should be able to use the Vivado programming tools to identify the FPGA and program a bitstream using the standard procedures outlined in Xilinx documentation (as well as use the ChipScope ILA, etc).
We typically recommend stopping the boot process in u-Boot (hit return at the countdown), programming the FPGA, and then either using uBoot memory access commands for debugging or letting linux continue to boot.
Many of our customers just upload the binary version of their bitstream to the filesystem and use the JTAG interface strictly for debugging.
We don't have any specific linux drivers for the PCIe interface (beyond the basic PCIe driver available from TI). We generally map physical memory to user space using the TI CMEM tool and program the FPGA to DMA-master data to that buffer which then can be accessed in user space. I believe there is an example of that described here:
With regards,
Mike
