Mity CPU Platforms » MitySOM-AM57X

Hi Sandeep,

As mentioned in the datasheet, all of the VDDSHVx pins with the exception of VDDSHV8 (for the MMC/SD interface) are connected to 1.8V on the MitySOM-AM57x.

You will need to use 1.8V compatible IO PHY on the PR2_MII0 and PR2_MII1 signals. You cannot use a pull-up to 3.3V, this will drive the AM57x input pins above specification and the AM57x will not be able to drive the output levels to the required input specification of the PHY. Pull-ups will not work and may damage the SOM.

I would strongly recommend using an ethernet PHY that supports 1.8V IO. If you must use DP83640, you will need to add level converters and ensure that the group delays through the converter will still allow the interface to meet the MII/RMII timing specifications on both the Tx and Rx side of the interface (e.g., at the AM57x as well as at the PHY interface of the MII/RMII interface). Critical Link does not recommend using DP83640 for this application / interface.

With regards,
Mike

Hi Michael,

We are planned to do our ethernet design with IEEE 1588 PTP hardware support with RJ45 and Fibre communication.
But since there is this IO level voltage differences we are planning to design the circuit with DP83822 Phy.
By referring the datasheet of DP83822, we can see that it will support IEEE 1588 PTP (Start of frame detect for IEEE 1588 time stamp) and also Fibre optic communication.
Also we are planning to integrate an additional DP83640 PHY IC (with voltage level translator IC SN74AXC8T245) sharing the TX and RX signals with one of the DP83822 IC (For the testing purpose).

Do you have any suggestion for the above mentioned points.

Thanks and regards
Sandeep S

Hi,

For testing IEEE 1588 H/W time stamp application, we included DP83640 in our circuit. Since DP83640 doesn't have 1.8V I/O level, we used Voltage level converters TXS0104E (Bidirectional, Push-pull and Open drain compatible) and SN74AXC8T245PWR (Uni directional). Please have a look at the schematic and let us know if you have any suggestions or corrections to be made.
Here I am attaching the schematic diagram of DP83640 design with RJ45/SFP module communication.

Thanks, and regards.
Sandeep S