Activity
From 01/17/2011 to 02/15/2011
01/28/2011
- GG 09:12 AM Software Development: RE: Where can I get the files listed on the DSPLink Hello World wiki?
- Hi Ms. Begley,
We're currently in the process of working on an automated release process for these files, so for now I've sent you an email with the necessary files attached.
Please let us know if you have any further questions or ...
01/27/2011
- Hi there!
Sorry, I seem to be missing something. Where can I find the files listed on the http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Hello_World wiki page (arm_main.cpp, libdsp.so, dsplink.patch, etc)? ...
01/22/2011
- MW 08:06 AM FPGA Development: RE: OMAP-L138 EMA_WE vs. EMA_A_RW documentation descrepancy, usage
- Yes. The revision I was looking at was indeed old. I don't know why the RNW pin isn't working for you. You might try posting to TI's E2E "OMAP-L Support Forum":http://e2e.ti.com/support/dsp/omap_applications_processors/f/42.aspx as th...
01/21/2011
- DO 05:37 PM FPGA Development: RE: OMAP-L138 EMA_WE vs. EMA_A_RW documentation descrepancy, usage
- Is there a chance you're looking at an older version of the document? The current version at the link you provided doesn't list that signal in table 2, but rather in table 3 "EMIFA Pins Specific to Asynchronous Memory", which should be O...
- MW 01:48 PM FPGA Development: RE: OMAP-L138 EMA_WE vs. EMA_A_RW documentation descrepancy, usage
- Ah. Sorry.
According to the "EMIFA Users Guide":http://www.ti.com/litv/pdf/sprufl6f, the EMA_A_RNW is only shown as being active for SDRAM control mode. (Table 2). It may not function for straight ASYNC RAM mode.
-Mike
- DK 01:36 PM FPGA Development: RE: OMAP-L138 EMA_WE vs. EMA_A_RW documentation descrepancy, usage
- Mike,
I understand the pin muxing requirements during the FPGA loading process versus normal operation. My question is do I need to configure any other registers besides PINMUX7 to enable ENA_RNW functionality.
Thanks,
Dave - MW 01:30 PM FPGA Development: RE: OMAP-L138 EMA_WE vs. EMA_A_RW documentation descrepancy, usage
- Hi David,
The EMA_RNW signal needs to be configured as a GPIO during an FPGA program cycle (see the fpga_ctrl.c file in the ARM drivers) as it is used for controlling the R/W signal of the configuration data on the FPGA during slave s... - DK 12:08 PM FPGA Development: RE: OMAP-L138 EMA_WE vs. EMA_A_RW documentation descrepancy, usage
- Mike,
FYI I am providing software support for Dene and have reconfigured the pin-mux setting for GP3[9] from GPIO to EMA_RNW (i.e. PINMUX7[27:24] = 1). However it appears that this signal isn't toggling when I read and write the same... - DK 04:41 PM Software Development: RE: Loading FPGA
- Mike,
The other issue is now resolved; our HW designer rebuilt the Xilinx image per your instructions which fixed the problem. We are now able to load our custom .bit images.
Thanks,
Dave - DK 04:17 PM Software Development: RE: Loading FPGA
- Mike,
You are correct and it looks like I have everything that I need.
Thank Again!
Dave
>>>>>>>>>> Directory /etc/rc5.d contained the following link:
lrwxrwxrwx 1 root root 14 May 8 20:58 S22fpga -> ../i... - MW 03:37 PM Software Development: RE: Loading FPGA
- Hi Dave,
"/etc/rc5.d" should be a directory. It should not be empty. Below is a listing of this directory for a unit I have here. It includes several key startup scripts... - DK 03:07 PM Software Development: RE: Loading FPGA
- Mike,
The file "/etc/rc5.d" is present but empty. Let me know if you have any other suggestions.
Thanks,
Dave - MW 01:33 PM Software Development: RE: Loading FPGA
- Ok,
Perhaps CL helped someone out there with this. The scripts for loading at runlevel 5 should be contained in /etc/rc5.d. Try searching there. This is how we recommend loading up the fpga (at runlevel 5), but we don't ship units... - DK 01:30 PM Software Development: RE: Loading FPGA
- Mike,
Thanks for your response. I didn't configure the board to load the FPGA and it isn't performed during u-boot. It appears to be performed during Linux INIT runlevel 5, see boot messages below. Any thoughts?
Thanks,
Dave - MW 01:18 PM Software Development: RE: Loading FPGA
- Hi David,
On 1), I suspect that the FPGA bin image may not be getting generated correctly. If you have a bit file, you can run the command referenced on "this page":http://support.criticallink.com/redmine/projects/arm9-platforms/wiki... - DK 12:57 PM Software Development: RE: Loading FPGA
- Mike,
I have built fpga_ctrl.ko from the source snapshot and am using program_fpga.sh to load the Xilinx FPGA. I have two questions below:
1) DONE is asserted if I load IndustrialIO.bin; however the DONE LED isn't asserted if I us... - MW 03:42 PM Software Development: RE: u-boot build question
- Dave,
Sorry about the delay on this response.
Under ubuntu 10.04, you need to install the "uboot-mkimage" package. E.G.:
01/19/2011
- DK 07:54 PM Software Development: RE: How Do I Get SD Memory Working for Critical Link Carrier Board From Linux
- Mike,
Thanks for your help and sorry for the late response. I determined that SD cards worked on the CriticalLink carrier board but not on our custom board. Everything is working fine on our board as the problem was due to a couple ... - GG 05:22 PM Software Development: RE: JTAG setup for CCSv3?
- Hi Mr. Szuch,
Blackhawk provides drivers for connecting to the OMAP-L138. This will give you the option for connecting to the C674X core.
\Greg Gluszek
01/17/2011
- DV 01:53 PM Software Development: RE: I2C Board Support Package
- Mike,
As John pointed out our problem was with the hardware. My problem was insufficient understanding of what I2C things were on the daughter card and which were on the custom board. However, you comment is extremely useful, as (once...