From 10/26/2014 to 11/24/2014
- 09:23 AM Software Development: RE: inotify issue
- This is a non-problem. It is working fine. Sorry for the trouble.
- 09:12 AM Software Development: RE: inotify issue
- Could you provide some example code that shows the problem you are having? Also need a better explanation of what pro...
- 07:31 AM Software Development: RE: inotify issue
- My mistake. Cut and paste error. The kernel is 2.6.34-RC1.
- Trying to get inotify to execute properly from inside my application code. I am using linux kernel 2.24-RC1.
- 05:16 PM Software Development: RE: FPGA configuration via u-Boot problem
- You can also use the promgen command to generate a bin file from a bit:
promgen -w -p bin -u 0 filename.bit -o fil...
- 07:29 AM FPGA Development: RE: PlanAhead issue
- For ISE (and I think ISE / PlanAhead are still the tools for Spartan 6, as the Vivado tools are for 7 series and high...
Why at creation of the project in PlanAhead 14.7 for the chip xc6slx45csg324-3 it is not possible to specify Tem...
- 07:51 AM Software Development: RE: FPGA configuration via u-Boot problem
I solved the problem.
It's important that the FPGA config file <fpga>.bin file was created correctly.
- Hi all,
I have a problem with the configuration of the FPGA and booting linux.
I followed the instructions from...
- 01:52 PM Software Development: RE: Real time SATA writes
- Hi Mary,
As you suspected in your original post, it is likely that when you are calling fwrite, in some cases the ...
- 01:04 PM Software Development: RE: Real time SATA writes
- After further testing and setting optimization, I have narrowed down the delay:
The call to fwrite() normally take...
I'm using MityDSP-L138F Board. As will ensure that the generated clock signal to FPGA?
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