Activity
From 06/19/2019 to 07/18/2019
07/18/2019
- 06:00 AM Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)
- Hi, thanks for reply!
Two follow up questions:
Concerning "you may want to look at some of the DSPlink or syslink c...
07/17/2019
- 03:04 PM Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)
- Note if your writing your own bare-metal communication you may want to look at some of the DSPlink or syslink code as...
- 02:05 PM Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)
- Thanks for the prompt reply!
I'm thinking about shared RAM that ARM user space linux driver will be able to mmap in ... - 02:01 PM Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal)
- Could you provide more information on what is suitable for your project?
- Hi,
I'd like to use MityDSPL138 kit in order to develop ARM(Linux) - DSP (bare-metal) data exchange over shared memo...
07/08/2019
- Hi,
I have a custom board with
-- MityDspl-138F module (with FPGA)
-- No Ethernet port
-- UART,USB,SD CARD int... - 10:05 AM Software Development: RE: uPP receive clock lower limitation in SDR (Single Data Rate mode)
- Thanks Greg for your reply and sorry for the late reply.
I will forward your response to our FPGA team. They are u...
06/24/2019
- 04:38 PM Software Development: RE: uPP receive clock lower limitation in SDR (Single Data Rate mode)
- Hi Vivek,
I believe the datasheet is saying that regardless of whether the clock is being used as DDR or SDR the ...
06/21/2019
- Hi,
I have a custom board with
-- MityDspl-138F module (with FPGA)
-- No Ethernet port
-- UART,USB,SD CARD int...
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