Activity
From 10/17/2013 to 11/15/2013
11/14/2013
- 02:39 PM FPGA Development: RE: Input/Output interfacing
- Thanks Mike,
I was able to export the signals I wanted and they now show up in Pin Planner.
Is it in general ok to ...
11/13/2013
- 01:41 PM FPGA Development: RE: Input/Output interfacing
- The FPGA ball numbers can be mapped to the edge connector via Table 7 in the "datasheet":http://www.mitydsp.com/image...
11/12/2013
- 07:03 PM FPGA Development: RE: Input/Output interfacing
- Also, I don't know if I have seen a file which shows which physical pins on the FPGA end up on which physical connect...
- 07:01 PM FPGA Development: RE: Input/Output interfacing
- Hi Dan
Yes, I have done exactly as you described.
I haven't worked with the Pin Planner as of yet, so I'll take a l... - 05:49 PM FPGA Development: RE: Input/Output interfacing
- Hi Richard,
I'm guessing you've created a component with a conduit for these external signals and you've exported ... - I have built a custom component in QSYS as a memory-mapped avalon slave and been able to interface it
correctly so t...
10/18/2013
- 12:10 PM Software Development: RE: Design examples
- Right. After a little digging I figured out that QSYS does the heavy lifting of
configuring the protocol glue logic... - 10:35 AM Software Development: RE: Design examples
- I'm glad you're over the hurdle, Rich. We don't have a formal tutorial yet, other than the sample project included wi...
- 10:20 AM Software Development: RE: Moving rbf file from host to dev-board
- Hi Rich,
You'll need to SCP the RBF over, I'm pretty sure FTP wasn't enabled by default. But I believe you will ne...
10/17/2013
- I have created a new rbf file with some custom logic added which I built using QSYS,
and converted from SOF format t... - 06:26 PM Software Development: RE: Design examples
- Ok, I was able to build a system with a new component that I created in QSYS
and added some custom VHDL logic to for...
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