Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

Hi Richard,

I'm guessing you've created a component with a conduit for these external signals and you've exported this conduit through qsys to your top level entity, is this assumption correct? If it is then you can use the pin planner to connect these signals to the physical pins, Assignments->Pin Planner. If you've done an Analysis & Synthesis then your new signals should be in the Pin Planner and you'll have to tell it a location and the I/O standard to use.

This is also doable in a tcl script.
For example
set_location_assignment PIN_AH21 -to HSMC1_D0
which will place HSMC1_D0 from the example project at pin PIN_AH21.

I've attached a TCL file that will setup the assignments for the HSMC pins in our example that came with the VM.

Hope this helps,
Dan

Hi Dan
Yes, I have done exactly as you described.
I haven't worked with the Pin Planner as of yet, so I'll take a look at that tomorrow.

So if I understand correctly, after I do a successfule Analysis and Synthesis step, the signals I've exported via conduits defined in QSYS will appear in the Pin Planner and then it's a matter of deciding which physical pins should be assigned to the constituent signals for the conduits I want to route to the outside world. Then do a final compile of the whole project and the signals will then appear on the appropriate pins?

Thanks!
Rich

Also, I don't know if I have seen a file which shows which physical pins on the FPGA end up on which physical connectors/pins on the carrier board.
Can you point me in the right direction?

Thanks!

The FPGA ball numbers can be mapped to the edge connector via Table 7 in the datasheet.

The devkit baseboard schematic is here.

We're trying to get a better cross reference or table or something, but those two documents should allow you to make the mappings you need.

I will post back when we have a better solution.

-Mike

Thanks Mike,
I was able to export the signals I wanted and they now show up in Pin Planner.
Is it in general ok to retask signals in the 5CSX_IO class?

For example, I see that on Module Pin Number 60 corresponding to CYCLONE pin AH26 there is a schematic net name assigned:
B4A_TX_B76n/DQ8B/B_DQ35 which is connected to signal HSMC2_PRSNT_n on the baseboard schematic.
It appears this signal goes to the Partial HSMC connector pin 160 and has an LED attached to it.

In Pin Planner is it ok to simply disconnect the assignment already there for pin AH26
and assign it to my own signal, and so forth?

Another related question:

Are all the predefined signals on the HSMC connectors there to allow 3rd party devices to connect to the carrier board,
and use some predefined IP core module to provide the interface logic and so forth?

Thanks again,
Rich

Hi Rich,

You need to be careful with the pin assignments. If you change an assignment that is by default controlled by the HPS subsystem to FPGA fabric (or vice-versa) you will need to regenerate the Altera "Pre-Loader" (first stage bootloader loaded by ROM bootloader, which programs the "magic" in the scan manager for the pin-mux settings). If you aren't too comfortable with that flow, I'd recommend running through the Cyclone V or Arria SOC online architecture tutorials to get the idea.

The HSMC definition is a "standard" that defines a reasonably common pin out to support various types of I/O. Yes, ideally you should be able to buy an off-the-shelf HSMC card (ADC circuit, or perhaps video input/output, etc.) and get a VHDL "driver" core to plumb it in. We haven't really done the yet with anything beyond a basic breakout connector. But many other Altera devkits use this approach with success. you should be able to Google from HSMC boards that you could purchase....

-Mike