Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

11/14/2013

02:39 PM FPGA Development: RE: Input/Output interfacing

Thanks Mike,
I was able to export the signals I wanted and they now show up in Pin Planner.
Is it in general ok to ... Rich Bagdazian

11/13/2013

01:41 PM FPGA Development: RE: Input/Output interfacing

The FPGA ball numbers can be mapped to the edge connector via Table 7 in the "datasheet":http://www.mitydsp.com/image... Michael Williamson

11/12/2013

07:03 PM FPGA Development: RE: Input/Output interfacing

Also, I don't know if I have seen a file which shows which physical pins on the FPGA end up on which physical connect... Rich Bagdazian

07:01 PM FPGA Development: RE: Input/Output interfacing

Hi Dan
Yes, I have done exactly as you described.
I haven't worked with the Pin Planner as of yet, so I'll take a l... Rich Bagdazian

05:49 PM FPGA Development: RE: Input/Output interfacing

Hi Richard,
I'm guessing you've created a component with a conduit for these external signals and you've exported ... Daniel Vincelette

04:47 PM FPGA Development: Input/Output interfacing

I have built a custom component in QSYS as a memory-mapped avalon slave and been able to interface it
correctly so t... Rich Bagdazian